tm-hppa.h

arm-linux-gcc编译器

/* Parameters for execution on any Hewlett-Packard PA-RISC machine.
   Copyright 1986, 1987, 1989-1993, 1995, 1999, 2000 Free Software Foundation, Inc. 

   Contributed by the Center for Software Science at the
   University of Utah ([e-mail]).

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

/* Forward declarations of some types we use in prototypes */

struct frame_info;
struct frame_saved_regs;
struct value;
struct type;
struct inferior_status;

/* Target system byte order. */

#define	TARGET_BYTE_ORDER	BIG_ENDIAN

/* By default assume we don't have to worry about software floating point.  */
#ifndef SOFT_FLOAT
#define SOFT_FLOAT 0
#endif

/* Get at various relevent fields of an instruction word. */

#define MASK_5 0x1f
#define MASK_11 0x7ff
#define MASK_14 0x3fff
#define MASK_21 0x1fffff

/* This macro gets bit fields using HP's numbering (MSB = 0) */
#ifndef GET_FIELD
#define GET_FIELD(X, FROM, TO) \
  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
#endif

/* Watch out for NaNs */

#define IEEE_FLOAT

/* On the PA, any pass-by-value structure > 8 bytes is actually
   passed via a pointer regardless of its type or the compiler
   used.  */

#define REG_STRUCT_HAS_ADDR(gcc_p,type) \
  (TYPE_LENGTH (type) > 8)

/* Offset from address of function to start of its code.
   Zero on most machines.  */

#define FUNCTION_START_OFFSET 0

/* Advance PC across any function entry prologue instructions
   to reach some "real" code.  */

extern CORE_ADDR hppa_skip_prologue PARAMS ((CORE_ADDR));
#define SKIP_PROLOGUE(pc) (hppa_skip_prologue (pc))

/* If PC is in some function-call trampoline code, return the PC
   where the function itself actually starts.  If not, return NULL.  */

#define	SKIP_TRAMPOLINE_CODE(pc) skip_trampoline_code (pc, NULL)
extern CORE_ADDR skip_trampoline_code PARAMS ((CORE_ADDR, char *));

/* Return non-zero if we are in an appropriate trampoline. */

#define IN_SOLIB_CALL_TRAMPOLINE(pc, name) \
   in_solib_call_trampoline (pc, name)
extern int in_solib_call_trampoline PARAMS ((CORE_ADDR, char *));

#define IN_SOLIB_RETURN_TRAMPOLINE(pc, name) \
  in_solib_return_trampoline (pc, name)
extern int in_solib_return_trampoline PARAMS ((CORE_ADDR, char *));

/* Immediately after a function call, return the saved pc.
   Can't go through the frames for this because on some machines
   the new frame is not set up until the new function executes
   some instructions.  */

#undef	SAVED_PC_AFTER_CALL
#define SAVED_PC_AFTER_CALL(frame) saved_pc_after_call (frame)
extern CORE_ADDR saved_pc_after_call PARAMS ((struct frame_info *));

/* Stack grows upward */
#define INNER_THAN(lhs,rhs) ((lhs) > (rhs))

/* elz: adjust the quantity to the next highest value which is 64-bit aligned.
   This is used in valops.c, when the sp is adjusted.
   On hppa the sp must always be kept 64-bit aligned */

#define STACK_ALIGN(arg) ( ((arg)%8) ? (((arg)+7)&-8) : (arg))
#define NO_EXTRA_ALIGNMENT_NEEDED 1

/* Sequence of bytes for breakpoint instruction.  */

#define BREAKPOINT {0x00, 0x01, 0x00, 0x04}
#define BREAKPOINT32 0x10004

/* Amount PC must be decremented by after a breakpoint.
   This is often the number of bytes in BREAKPOINT
   but not always.

   Not on the PA-RISC */

#define DECR_PC_AFTER_BREAK 0

/* Sometimes we may pluck out a minimal symbol that has a negative
   address.

   An example of this occurs when an a.out is linked against a foo.sl.
   The foo.sl defines a global bar(), and the a.out declares a signature
   for bar().  However, the a.out doesn't directly call bar(), but passes
   its address in another call.

   If you have this scenario and attempt to "break bar" before running,
   gdb will find a minimal symbol for bar() in the a.out.  But that
   symbol's address will be negative.  What this appears to denote is
   an index backwards from the base of the procedure linkage table (PLT)
   into the data linkage table (DLT), the end of which is contiguous
   with the start of the PLT.  This is clearly not a valid address for
   us to set a breakpoint on.

   Note that one must be careful in how one checks for a negative address.
   0xc0000000 is a legitimate address of something in a shared text
   segment, for example.  Since I don't know what the possible range
   is of these "really, truly negative" addresses that come from the
   minimal symbols, I'm resorting to the gross hack of checking the
   top byte of the address for all 1's.  Sigh.
 */
#define PC_REQUIRES_RUN_BEFORE_USE(pc) \
  (! target_has_stack && (pc & 0xFF000000))

/* return instruction is bv r0(rp) or bv,n r0(rp) */

#define ABOUT_TO_RETURN(pc) ((read_memory_integer (pc, 4) | 0x2) == 0xE840C002)

/* Say how long (ordinary) registers are.  This is a piece of bogosity
   used in push_word and a few other places; REGISTER_RAW_SIZE is the
   real way to know how big a register is.  */

#define REGISTER_SIZE 4

/* Number of machine registers */

#define NUM_REGS 128

/* Initializer for an array of names of registers.
   There should be NUM_REGS strings in this initializer.
   They are in rows of eight entries  */

#define REGISTER_NAMES	\
 {"flags",  "r1",      "rp",      "r3",    "r4",     "r5",      "r6",     "r7",    \
  "r8",     "r9",      "r10",     "r11",   "r12",    "r13",     "r14",    "r15",   \
  "r16",    "r17",     "r18",     "r19",   "r20",    "r21",     "r22",    "r23",   \
  "r24",    "r25",     "r26",     "dp",    "ret0",   "ret1",    "sp",     "r31",   \
  "sar",    "pcoqh",   "pcsqh",   "pcoqt", "pcsqt",  "eiem",    "iir",    "isr",   \
  "ior",    "ipsw",    "goto",    "sr4",   "sr0",    "sr1",     "sr2",    "sr3",   \
  "sr5",    "sr6",     "sr7",     "cr0",   "cr8",    "cr9",     "ccr",    "cr12",  \
  "cr13",   "cr24",    "cr25",    "cr26",  "mpsfu_high","mpsfu_low","mpsfu_ovflo","pad",\
  "fpsr",    "fpe1",   "fpe2",    "fpe3",  "fpe4",   "fpe5",    "fpe6",   "fpe7",  \
  "fr4",     "fr4R",   "fr5",     "fr5R",  "fr6",    "fr6R",    "fr7",    "fr7R",  \
  "fr8",     "fr8R",   "fr9",     "fr9R",  "fr10",   "fr10R",   "fr11",   "fr11R", \
  "fr12",    "fr12R",  "fr13",    "fr13R", "fr14",   "fr14R",   "fr15",   "fr15R", \
  "fr16",    "fr16R",  "fr17",    "fr17R", "fr18",   "fr18R",   "fr19",   "fr19R", \
  "fr20",    "fr20R",  "fr21",    "fr21R", "fr22",   "fr22R",   "fr23",   "fr23R", \
  "fr24",    "fr24R",  "fr25",    "fr25R", "fr26",   "fr26R",   "fr27",   "fr27R", \
  "fr28",    "fr28R",  "fr29",    "fr29R", "fr30",   "fr30R",   "fr31",   "fr31R"}

/* Register numbers of various important registers.
   Note that some of these values are "real" register numbers,
   and correspond to the general registers of the machine,
   and some are "phony" register numbers which are too large
   to be actual register numbers as far as the user is concerned
   but do serve to get the desired values when passed to read_register.  */

#define R0_REGNUM 0		/* Doesn't actually exist, used as base for
				   other r registers.  */
#define FLAGS_REGNUM 0		/* Various status flags */
#define RP_REGNUM 2		/* return pointer */
#define FP_REGNUM 3		/* Contains address of executing stack */
				/* frame */
#define SP_REGNUM 30		/* Contains address of top of stack */
#define SAR_REGNUM 32		/* Shift Amount Register */
#define IPSW_REGNUM 41		/* Interrupt Processor Status Word */
#define PCOQ_HEAD_REGNUM 33	/* instruction offset queue head */
#define PCSQ_HEAD_REGNUM 34	/* instruction space queue head */
#define PCOQ_TAIL_REGNUM 35	/* instruction offset queue tail */
#define PCSQ_TAIL_REGNUM 36	/* instruction space queue tail */
#define EIEM_REGNUM 37		/* External Interrupt Enable Mask */
#define IIR_REGNUM 38		/* Interrupt Instruction Register */
#define IOR_REGNUM 40		/* Interrupt Offset Register */
#define SR4_REGNUM 43		/* space register 4 */
#define RCR_REGNUM 51		/* Recover Counter (also known as cr0) */
#define CCR_REGNUM 54		/* Coprocessor Configuration Register */
#define TR0_REGNUM 57		/* Temporary Registers (cr24 -> cr31) */
#define CR27_REGNUM 60		/* Base register for thread-local storage, cr27 */
#define FP0_REGNUM 64		/* floating point reg. 0 (fspr) */
#define FP4_REGNUM 72

#define ARG0_REGNUM 26		/* The first argument of a callee. */
#define ARG1_REGNUM 25		/* The second argument of a callee. */
#define ARG2_REGNUM 24		/* The third argument of a callee. */
#define ARG3_REGNUM 23		/* The fourth argument of a callee. */

/* compatibility with the rest of gdb. */
#define PC_REGNUM PCOQ_HEAD_REGNUM
#define NPC_REGNUM PCOQ_TAIL_REGNUM

/*
 * Processor Status Word Masks
 */

#define PSW_T   0x01000000	/* Taken Branch Trap Enable */
#define PSW_H   0x00800000	/* Higher-Privilege Transfer Trap Enable */
#define PSW_L   0x00400000	/* Lower-Privilege Transfer Trap Enable */
#define PSW_N   0x00200000	/* PC Queue Front Instruction Nullified */
#define PSW_X   0x00100000	/* Data Memory Break Disable */
#define PSW_B   0x00080000	/* Taken Branch in Previous Cycle */
#define PSW_C   0x00040000	/* Code Address Translation Enable */
#define PSW_V   0x00020000	/* Divide Step Correction */
#define PSW_M   0x00010000	/* High-Priority Machine Check Disable */
#define PSW_CB  0x0000ff00	/* Carry/Borrow Bits */
#define PSW_R   0x00000010	/* Recovery Counter Enable */
#define PSW_Q   0x00000008	/* Interruption State Collection Enable */
#define PSW_P   0x00000004	/* Protection ID Validation Enable */
#define PSW_D   0x00000002	/* Data Address Translation Enable */
#define PSW_I   0x00000001	/* External, Power Failure, Low-Priority */
				/* Machine Check Interruption Enable */

/* When fetching register values from an inferior or a core file,
   clean them up using this macro.  BUF is a char pointer to
   the raw value of the register in the registers[] array.  */

#define	CLEAN_UP_REGISTER_VALUE(regno, buf) \
  do {	\
    if ((regno) == PCOQ_HEAD_REGNUM || (regno) == PCOQ_TAIL_REGNUM) \
      (buf)[sizeof(CORE_ADDR) -1] &= ~0x3; \
  } while (0)

/* Define DO_REGISTERS_INFO() to do machine-specific formatting
   of register dumps. */

#define DO_REGISTERS_INFO(_regnum, fp) pa_do_registers_info (_regnum, fp)
extern void pa_do_registers_info PARAMS ((int, int));

#if 0
#define STRCAT_REGISTER(regnum, fpregs, stream, precision) pa_do_strcat_registers_info (regnum, fpregs, stream, precision)
extern void pa_do_strcat_registers_info (int, int, struct ui_file *, enum precision_type);
#endif

/* PA specific macro to see if the current instruction is nullified. */
#ifndef INSTRUCTION_NULLIFIED