📄 fifo_outputbuffer.vhd
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SIGNAL wire_b_full_w_lg_Q74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_b_full_w_lg_Q78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_b_full_w_lg_Q90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL b_non_empty : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_b_non_empty_w_lg_w_lg_Q87w88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_b_non_empty_w_lg_Q87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_count_usedw_cnt_en : STD_LOGIC;
SIGNAL wire_fifo_state_w_lg_valid_wreq5w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_count_usedw_q : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_fifo_state_w_lg_w_lg_is_almost_empty682w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_fifo_state_w_lg_is_almost_empty682w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_fifo_state_w_lg_rreq69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_fifo_state_w_lg_sclr72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_fifo_state_w_lg_wreq81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_fifo_state_w_lg_sclr84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_fifo_state_w_lg_sclr77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL equal_af1 : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL equal_one : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL is_almost_empty0 : STD_LOGIC;
SIGNAL is_almost_empty1 : STD_LOGIC;
SIGNAL is_almost_empty2 : STD_LOGIC;
SIGNAL is_almost_empty3 : STD_LOGIC;
SIGNAL is_almost_empty4 : STD_LOGIC;
SIGNAL is_almost_empty5 : STD_LOGIC;
SIGNAL is_almost_empty6 : STD_LOGIC;
SIGNAL is_almost_full0 : STD_LOGIC;
SIGNAL is_almost_full1 : STD_LOGIC;
SIGNAL is_almost_full2 : STD_LOGIC;
SIGNAL is_almost_full3 : STD_LOGIC;
SIGNAL is_almost_full4 : STD_LOGIC;
SIGNAL is_almost_full5 : STD_LOGIC;
SIGNAL is_almost_full6 : STD_LOGIC;
SIGNAL usedw : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL valid_rreq : STD_LOGIC;
SIGNAL valid_wreq : STD_LOGIC;
COMPONENT fifo_Outputbuffer_cntr_ac7
PORT
(
aclr : IN STD_LOGIC := '0';
clock : IN STD_LOGIC;
cnt_en : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
sclr : IN STD_LOGIC := '0';
updown : IN STD_LOGIC := '1'
);
END COMPONENT;
BEGIN
wire_fifo_state_w_lg_w_lg_is_almost_empty682w83w(0) <= wire_fifo_state_w_lg_is_almost_empty682w(0) AND wire_fifo_state_w_lg_wreq81w(0);
wire_fifo_state_w_lg_is_almost_empty682w(0) <= is_almost_empty6 AND rreq;
wire_fifo_state_w_lg_rreq69w(0) <= NOT rreq;
wire_fifo_state_w_lg_sclr72w(0) <= NOT sclr;
wire_fifo_state_w_lg_wreq81w(0) <= NOT wreq;
wire_fifo_state_w_lg_sclr84w(0) <= sclr OR wire_fifo_state_w_lg_w_lg_is_almost_empty682w83w(0);
wire_fifo_state_w_lg_sclr77w(0) <= sclr OR rreq;
equal_af1 <= ( "0" & "0" & "0" & "0" & "0" & "0" & "0");
equal_one <= ( "1" & "1" & "1" & "1" & "1" & "1" & "0");
is_almost_empty0 <= (usedw(0) XOR equal_one(0));
is_almost_empty1 <= ((usedw(1) XOR equal_one(1)) AND is_almost_empty0);
is_almost_empty2 <= ((usedw(2) XOR equal_one(2)) AND is_almost_empty1);
is_almost_empty3 <= ((usedw(3) XOR equal_one(3)) AND is_almost_empty2);
is_almost_empty4 <= ((usedw(4) XOR equal_one(4)) AND is_almost_empty3);
is_almost_empty5 <= ((usedw(5) XOR equal_one(5)) AND is_almost_empty4);
is_almost_empty6 <= ((usedw(6) XOR equal_one(6)) AND is_almost_empty5);
is_almost_full0 <= (usedw(0) XOR equal_af1(0));
is_almost_full1 <= ((usedw(1) XOR equal_af1(1)) AND is_almost_full0);
is_almost_full2 <= ((usedw(2) XOR equal_af1(2)) AND is_almost_full1);
is_almost_full3 <= ((usedw(3) XOR equal_af1(3)) AND is_almost_full2);
is_almost_full4 <= ((usedw(4) XOR equal_af1(4)) AND is_almost_full3);
is_almost_full5 <= ((usedw(5) XOR equal_af1(5)) AND is_almost_full4);
is_almost_full6 <= ((usedw(6) XOR equal_af1(6)) AND is_almost_full5);
usedw <= wire_count_usedw_q;
usedw_out <= usedw;
valid_rreq <= rreq;
valid_wreq <= wreq;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN b_full <= '0';
ELSIF (clock = '1' AND clock'event) THEN b_full <= (wire_b_full_w_lg_Q79w(0) OR (wire_b_full_w_lg_w_lg_Q74w75w(0) AND (wire_fifo_state_w_lg_sclr72w(0) AND ((is_almost_full6 AND wreq) AND wire_fifo_state_w_lg_rreq69w(0)))));
END IF;
END PROCESS;
wire_b_full_w_lg_w_lg_Q74w75w(0) <= wire_b_full_w_lg_Q74w(0) AND b_non_empty;
wire_b_full_w_lg_Q79w(0) <= b_full AND wire_b_full_w_lg_Q78w(0);
wire_b_full_w_lg_Q91w(0) <= b_full AND wire_b_full_w_lg_Q90w(0);
wire_b_full_w_lg_Q74w(0) <= NOT b_full;
wire_b_full_w_lg_Q78w(0) <= b_full XOR wire_fifo_state_w_lg_sclr77w(0);
wire_b_full_w_lg_Q90w(0) <= b_full XOR sclr;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN b_non_empty <= '0';
ELSIF (clock = '1' AND clock'event) THEN b_non_empty <= ((wire_b_full_w_lg_Q91w(0) OR (wire_b_non_empty_w_lg_w_lg_Q87w88w(0) AND wire_fifo_state_w_lg_sclr72w(0))) OR (wire_b_full_w_lg_w_lg_Q74w75w(0) AND (wire_b_full_w_lg_w_lg_Q74w75w(0) XOR wire_fifo_state_w_lg_sclr84w(0))));
END IF;
END PROCESS;
wire_b_non_empty_w_lg_w_lg_Q87w88w(0) <= wire_b_non_empty_w_lg_Q87w(0) AND wreq;
wire_b_non_empty_w_lg_Q87w(0) <= NOT b_non_empty;
wire_count_usedw_cnt_en <= wire_fifo_state_w_lg_valid_wreq5w(0);
wire_fifo_state_w_lg_valid_wreq5w(0) <= valid_wreq XOR valid_rreq;
count_usedw : fifo_Outputbuffer_cntr_ac7
PORT MAP (
aclr => aclr,
clock => clock,
cnt_en => wire_count_usedw_cnt_en,
q => wire_count_usedw_q,
sclr => sclr,
updown => valid_wreq
);
END RTL; --fifo_Outputbuffer_a_fefifo_nce
--altdpram DEVICE_FAMILY="Cyclone" RDCONTROL_ACLR="OFF" RDCONTROL_REG="UNREGISTERED" SUPPRESS_MEMORY_CONVERSION_WARNINGS="ON" USE_EAB="ON" WIDTH=4 WIDTHAD=7 data inclock outclock outclocken q rdaddress wraddress wren
--VERSION_BEGIN 5.1 cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ VERSION_END
--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" INDATA_ACLR_A="NONE" OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" RDCONTROL_ACLR_B="NONE" RDCONTROL_REG_B="CLOCK0" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=4 WIDTH_B=4 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
--VERSION_BEGIN 5.1 cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ VERSION_END
LIBRARY cyclone;
USE cyclone.all;
--synthesis_resources = M4K 4
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fifo_Outputbuffer_altsyncram_0ga1 IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (6 DOWNTO 0) := (OTHERS => '1');
clock0 : IN STD_LOGIC := '1';
clock1 : IN STD_LOGIC := '1';
clocken1 : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
q_b : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
wren_a : IN STD_LOGIC := '0'
);
END fifo_Outputbuffer_altsyncram_0ga1;
ARCHITECTURE RTL OF fifo_Outputbuffer_altsyncram_0ga1 IS
ATTRIBUTE synthesis_clearbox : boolean;
ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
ATTRIBUTE ALTERA_ATTRIBUTE : string;
ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
SIGNAL wire_ram_block2a_0portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block2a_1portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block2a_2portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block2a_3portaaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block2a_0portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block2a_1portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block2a_2portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block2a_3portadatain : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block2a_portawe : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL wire_ram_block2a_0portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block2a_1portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block2a_2portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block2a_3portbaddr : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL wire_ram_block2a_0portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block2a_1portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block2a_2portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block2a_3portbdataout : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_ram_block2a_portbrewe : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL address_a_wire : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL address_b_wire : STD_LOGIC_VECTOR (6 DOWNTO 0);
COMPONENT cyclone_ram_block
GENERIC
(
CONNECTIVITY_CHECKING : STRING := "OFF";
DATA_INTERLEAVE_OFFSET_IN_BITS : NATURAL := 1;
DATA_INTERLEAVE_WIDTH_IN_BITS : NATURAL := 1;
INIT_FILE : STRING := "UNUSED";
INIT_FILE_LAYOUT : STRING := "UNUSED";
LOGICAL_RAM_NAME : STRING;
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
MIXED_PORT_FEED_THROUGH_MODE : STRING := "UNUSED";
OPERATION_MODE : STRING;
PORT_A_ADDRESS_CLEAR : STRING := "UNUSED";
PORT_A_ADDRESS_WIDTH : NATURAL := 1;
PORT_A_BYTE_ENABLE_CLEAR : STRING := "UNUSED";
PORT_A_BYTE_ENABLE_MASK_WIDTH : NATURAL := 1;
PORT_A_DATA_IN_CLEAR : STRING := "UNUSED";
PORT_A_DATA_OUT_CLEAR : STRING := "UNUSED";
PORT_A_DATA_OUT_CLOCK : STRING := "none";
PORT_A_DATA_WIDTH : NATURAL := 1;
PORT_A_FIRST_ADDRESS : NATURAL;
PORT_A_FIRST_BIT_NUMBER : NATURAL;
PORT_A_LAST_ADDRESS : NATURAL;
PORT_A_LOGICAL_RAM_DEPTH : NATURAL := 0;
PORT_A_LOGICAL_RAM_WIDTH : NATURAL := 0;
PORT_A_WRITE_ENABLE_CLEAR : STRING := "UNUSED";
PORT_B_ADDRESS_CLEAR : STRING := "UNUSED";
PORT_B_ADDRESS_CLOCK : STRING := "UNUSED";
PORT_B_ADDRESS_WIDTH : NATURAL := 1;
PORT_B_BYTE_ENABLE_CLEAR : STRING := "UNUSED";
PORT_B_BYTE_ENABLE_CLOCK : STRING := "UNUSED";
PORT_B_BYTE_ENABLE_MASK_WIDTH : NATURAL := 1;
PORT_B_DATA_IN_CLEAR : STRING := "UNUSED";
PORT_B_DATA_IN_CLOCK : STRING := "UNUSED";
PORT_B_DATA_OUT_CLEAR : STRING := "UNUSED";
PORT_B_DATA_OUT_CLOCK : STRING := "none";
PORT_B_DATA_WIDTH : NATURAL := 1;
PORT_B_FIRST_ADDRESS : NATURAL := 0;
PORT_B_FIRST_BIT_NUMBER : NATURAL := 0;
PORT_B_LAST_ADDRESS : NATURAL := 0;
PORT_B_LOGICAL_RAM_DEPTH : NATURAL := 0;
PORT_B_LOGICAL_RAM_WIDTH : NATURAL := 0;
PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR : STRING := "UNUSED";
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK : STRING := "UNUSED";
POWER_UP_UNINITIALIZED : STRING := "false";
RAM_BLOCK_TYPE : STRING;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "cyclone_ram_block"
);
PORT
(
clk0 : IN STD_LOGIC;
clk1 : IN STD_LOGIC := '0';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
portaaddr : IN STD_LOGIC_VECTOR(PORT_A_ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(PORT_A_BYTE_ENABLE_MASK_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
portadatain : IN STD_LOGIC_VECTOR(PORT_A_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
portadataout : OUT STD_LOGIC_VECTOR(PORT_A_DATA_WIDTH-1 DOWNTO 0);
portawe : IN STD_LOGIC := '0';
portbaddr : IN STD_LOGIC_VECTOR(PORT_B_ADDRESS_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
portbbyteenamasks : IN STD_LOGIC_VECTOR(PORT_B_BYTE_ENABLE_MASK_WIDTH-1 DOWNTO 0) := (OTHERS => '1');
portbdatain : IN STD_LOGIC_VECTOR(PORT_B_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
portbdataout : OUT STD_LOGIC_VECTOR(PORT_B_DATA_WIDTH-1 DOWNTO 0);
portbrewe : IN STD_LOGIC := '0'
);
END COMPONENT;
BEGIN
address_a_wire <= address_a;
address_b_wire <= address_b;
q_b <= ( wire_ram_block2a_3portbdataout(0) & wire_ram_block2a_2portbdataout(0) & wire_ram_block2a_1portbdataout(0) & wire_ram_block2a_0portbdataout(0));
wire_ram_block2a_portawe <= "1111";
wire_ram_block2a_portbrewe <= "1111";
wire_ram_block2a_0portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block2a_0portadatain(0) <= ( data_a(0));
wire_ram_block2a_0portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block2a_1portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block2a_1portadatain(0) <= ( data_a(1));
wire_ram_block2a_1portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block2a_2portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block2a_2portadatain(0) <= ( data_a(2));
wire_ram_block2a_2portbaddr <= ( address_b_wire(6 DOWNTO 0));
wire_ram_block2a_3portaaddr <= ( address_a_wire(6 DOWNTO 0));
wire_ram_block2a_3portadatain(0) <= ( data_a(3));
wire_ram_block2a_3portbaddr <= ( address_b_wire(6 DOWNTO 0));
ram_block2a_0 : cyclone_ram_block
GENERIC MAP (
CONNECTIVITY_CHECKING => "OFF",
LOGICAL_RAM_NAME => "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
OPERATION_MODE => "dual_port",
PORT_A_ADDRESS_CLEAR => "none",
PORT_A_ADDRESS_WIDTH => 7,
PORT_A_DATA_IN_CLEAR => "none",
PORT_A_DATA_WIDTH => 1,
PORT_A_FIRST_ADDRESS => 0,
PORT_A_FIRST_BIT_NUMBER => 0,
PORT_A_LAST_ADDRESS => 127,
PORT_A_LOGICAL_RAM_DEPTH => 128,
PORT_A_LOGICAL_RAM_WIDTH => 4,
PORT_A_WRITE_ENABLE_CLEAR => "none",
PORT_B_ADDRESS_CLEAR => "none",
PORT_B_ADDRESS_CLOCK => "clock1",
PORT_B_ADDRESS_WIDTH => 7,
PORT_B_DATA_OUT_CLEAR => "none",
PORT_B_DATA_OUT_CLOCK => "none",
PORT_B_DATA_WIDTH => 1,
PORT_B_FIRST_ADDRESS => 0,
PORT_B_FIRST_BIT_NUMBER => 0,
PORT_B_LAST_ADDRESS => 127,
PORT_B_LOGICAL_RAM_DEPTH => 128,
PORT_B_LOGICAL_RAM_WIDTH => 4,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
RAM_BLOCK_TYPE => "auto"
)
PORT MAP (
clk0 => clock0,
clk1 => clock1,
ena0 => wren_a,
ena1 => clocken1,
portaaddr => wire_ram_block2a_0portaaddr,
portadatain => wire_ram_block2a_0portadatain,
portawe => wire_ram_block2a_portawe(0),
portbaddr => wire_ram_block2a_0portbaddr,
portbdataout => wire_ram_block2a_0portbdataout,
portbrewe => wire_ram_block2a_portbrewe(0)
);
ram_block2a_1 : cyclone_ram_block
GENERIC MAP (
CONNECTIVITY_CHECKING => "OFF",
LOGICAL_RAM_NAME => "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
OPERATION_MODE => "dual_port",
PORT_A_ADDRESS_CLEAR => "none",
PORT_A_ADDRESS_WIDTH => 7,
PORT_A_DATA_IN_CLEAR => "none",
PORT_A_DATA_WIDTH => 1,
PORT_A_FIRST_ADDRESS => 0,
PORT_A_FIRST_BIT_NUMBER => 1,
PORT_A_LAST_ADDRESS => 127,
PORT_A_LOGICAL_RAM_DEPTH => 128,
PORT_A_LOGICAL_RAM_WIDTH => 4,
PORT_A_WRITE_ENABLE_CLEAR => "none",
PORT_B_ADDRESS_CLEAR => "none",
PORT_B_ADDRESS_CLOCK => "clock1",
PORT_B_ADDRESS_WIDTH => 7,
PORT_B_DATA_OUT_CLEAR => "none",
PORT_B_DATA_OUT_CLOCK => "none",
PORT_B_DATA_WIDTH => 1,
PORT_B_FIRST_ADDRESS => 0,
PORT_B_FIRST_BIT_NUMBER => 1,
PORT_B_LAST_ADDRESS => 127,
PORT_B_LOGICAL_RAM_DEPTH => 128,
PORT_B_LOGICAL_RAM_WIDTH => 4,
PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
RAM_BLOCK_TYPE => "auto"
)
PORT MAP (
clk0 => clock0,
clk1 => clock1,
ena0 => wren_a,
ena1 => clocken1,
portaaddr => wire_ram_block2a_1portaaddr,
portadatain => wire_ram_block2a_1portadatain,
portawe => wire_ram_block2a_portawe(1),
portbaddr => wire_ram_block2a_1portbaddr,
portbdataout => wire_ram_block2a_1portbdataout,
portbrewe => wire_ram_block2a_portbrewe(1)
);
ram_block2a_2 : cyclone_ram_block
GENERIC MAP (
CONNECTIVITY_CHECKING => "OFF",
LOGICAL_RAM_NAME => "ALTSYNCRAM",
MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
OPERATION_MODE => "dual_port",
PORT_A_ADDRESS_CLEAR => "none",
PORT_A_ADDRESS_WIDTH => 7,
PORT_A_DATA_IN_CLEAR => "none",
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