outputbuffer.vhd

RS的编码。最新的移动多媒体应用技术的源代码

-- ================================================================================
-- File: OutputBuffer.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.30.2006
-- Description:
-- Output Buffer is the last module in the project. It receive RS decoder's output
-- and then sent to user at a proper time controlled by source_ena port. The
-- structure of output buffer is similar with CP remove part.
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- ================================================================================

entity Outputbuffer is
	port
	(
		-- clock input
		clk: in std_logic;
		-- asynchroism clear input
		aclr: in std_logic;
		-- 10 bit width input and output data ports
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		-- simple ALTERA Atlantic interface ports
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end OutputBuffer;

-- ================================================================================

architecture structure of OutputBuffer is

-- --------------------------------------------------------------------------------

-- declarations

-- fifo declaration
-- 128 words * 4 bits
component fifo_Outputbuffer
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
	);
end component;
-- connection signals
signal outputFIFO: std_logic_vector (3 downto 0);
signal readEnaFIFO: std_logic;
signal usedwFIFO: std_logic_vector (6 downto 0);
signal usedwIntFIFO: natural range 0 to 128;
-- delay
signal readEnaFIFO_d: std_logic;

-- FSM state declaration
type FSM_state is
	(
		Reset, CountFIFO, ReadFIFO, ReadRAM
	);
-- state signal
signal state: FSM_state;

-- RAM declaration
-- 4 bits * 6 words
component ram_Outputbuffer
	PORT
	(
		aclr		: IN STD_LOGIC  := '0';
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
end component;
-- connection signals
signal outputRAM: std_logic_vector (3 downto 0);
signal writeEnaRAM: std_logic;
signal readEnaRAM: std_logic;
signal writeAddRAM: std_logic_vector (2 downto 0);
signal readAddRAM: std_logic_vector (2 downto 0);
signal writeAddIntRAM: natural range 0 to 5;
signal readAddIntRAM: natural range 0 to 5;
-- delay
signal readEnaRAM_d: std_logic;
signal readEnaRAM_d2: std_logic;

-- output data select
signal interval_data: std_logic_vector (3 downto 0);

-- interval interface signals
signal interval_sink_ena: std_logic;
signal interval_source_val: std_logic;
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;

-- delayed interface signals
signal interval_source_val_d: std_logic;
signal interval_source_sop_d: std_logic;
signal interval_source_eop_d: std_logic;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

-- fifo connection
u1: fifo_Outputbuffer port map
	(
		aclr => aclr, clock => clk,
		data => inputData, wrreq => sink_val,
		q => outputFIFO, rdreq => readEnaFIFO,
		usedw => usedwFIFO
	);
	
-- convert to integer
usedwIntFIFO <= to_integer(unsigned(usedwFIFO));

-- sink_ena
process(aclr,clk,usedwIntFIFO)
begin
	if aclr = '1' then
		interval_sink_ena <= '0';
	else
		if rising_edge(clk) then
			if usedwIntFIFO >= 122 then
				interval_sink_ena <= '0';
			else
				interval_sink_ena <= '1';
			end if;
		end if;
	end if;
end process;

-- delay readEnaFIFO
process(clk,readEnaFIFO)
begin
	if rising_edge(clk) then
		readEnaFIFO_d <= readEnaFIFO;
	end if;
end process;

-- RAM connection
u2: ram_OutputBuffer port map
	(
		aclr => aclr, clock => clk,
		data => outputFIFO, q => outputRAM,
		rdaddress => readAddRAM, rden => readEnaRAM,
		wraddress => writeAddRAM, wren => readEnaFIFO_d
	);

-- convert to std_logic_vector
readAddRAM <= std_logic_vector(to_unsigned(readAddIntRAM,3));
writeAddRAM <= std_logic_vector(to_unsigned(writeAddIntRAM,3));

-- FSM state transfer process
process(aclr,clk,usedwIntFIFO,writeAddIntRAM,readAddIntRAM)
begin
	if aclr = '1' then
		state <= reset;
	else
		if rising_edge(clk) then
			case state is
				when Reset =>
					state <= CountFIFO;
				when CountFIFO =>
					if usedwIntFIFO >= 6 then
						state <= ReadFIFO;
					end if;
				when ReadFIFO =>
					if writeAddIntRAM = 4 then -- shut down earlier
						state <= ReadRAM;
					end if;
				when ReadRAM =>
					if readAddIntRAM = 1 then
						state <= CountFIFO;
					end if;
			end case;
		end if;
	end if;
end process;

-- state functional controlling read FIFO/RAM enable
process(state,source_ena)
begin
	case state is
		when Reset =>
			readEnaFIFO <= '0';
			readEnaRAM <= '0';
		when CountFIFO =>
			readEnaFIFO <= '0';
			readEnaRAM <= '0';
		when ReadFIFO =>
			readEnaFIFO <= '1';
			readEnaRAM <= '0';
		when ReadRAM =>
			readEnaFIFO <= '0';
			if source_ena = '1' then
				readEnaRAM <= '1';
			else
				readEnaRAM <= '0';
			end if;
	end case;
end process;

-- reading from FIFO process
process(aclr,clk,readEnaFIFO_d)
begin
	if aclr = '1' then
		writeAddIntRAM <= 0;
	else
		if rising_edge(clk) then
			if readEnaFIFO_d = '1' then
				if writeAddIntRAM = 5 then
					writeAddIntRAM <= 0;
				else
					writeAddIntRAM <= writeAddIntRAM + 1;
				end if;
			else
				writeAddIntRAM <= 0;
			end if;
		end if;
	end if;
end process;

-- RAM reading process
process(aclr,clk,readEnaRAM)
begin
	if aclr = '1' then
		readAddIntRAM <= 0;
	else
		if rising_edge(clk) then
			if readEnaRAM = '1' then
				if readAddIntRAM = 1 then
					readAddIntRAM <= 0;
				else
					readAddIntRAM <= readAddIntRAM + 1;
				end if;
			else
				readAddIntRAM <= 0;
			end if;
		end if;
	end if;
end process;

-- delay readEnaRAM
process(clk,readEnaRAM)
begin
	if rising_edge(clk) then
		readEnaRAM_d <= readEnaRAM;
		readEnaRAM_d2 <= readEnaRAM_d;
	end if;
end process;

-- data select
process(readEnaRAM_d2, outputRAM)
begin
	if readEnaRAM_d2 = '1' then
		interval_data <= outputRAM;
	else
		interval_data <= "0000";
	end if;
end process;

-- generate interface signals
process(clk,readEnaRAM,readAddIntRAM)
begin
	if rising_edge(clk) then
		if readEnaRAM = '1' then
			interval_source_val <= '1';
			if readAddIntRAM = 0 then
				interval_source_sop <= '1';
				interval_source_eop <= '0';
			elsif readAddIntRAM = 1 then
				interval_source_sop <= '0';
				interval_source_eop <= '1';
			else
				interval_source_sop <= '0';
				interval_source_eop <= '0';
			end if;
		else
			interval_source_val <= '0';
			interval_source_sop <= '0';
			interval_source_eop <= '0';
		end if;
	end if;
end process;

-- delay
process(clk,interval_source_val,interval_source_sop,interval_source_eop)
begin
	if rising_edge(clk) then
		interval_source_val_d <= interval_source_val;
		interval_source_sop_d <= interval_source_sop;
		interval_source_eop_d <= interval_source_eop;
	end if;
end process;

-- synchronize output using falling edge
process(clk,interval_data,interval_source_val_d,
		interval_source_sop_d,interval_source_eop_d)
begin
	if falling_edge(clk) then -- using falling edge
		outputData <= interval_data;
		sink_ena <= interval_sink_ena;
		source_val <= interval_source_val_d;
		source_sop <= interval_source_sop_d;
		source_eop <= interval_source_eop_d;
	end if;
end process;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================================