constellation.vhd

RS的编码。最新的移动多媒体应用技术的源代码

-- ================================================================================
-- File: Constellation.vhd
-- Version: v1.1
-- Author: olivercamel
-- Date: 4.17.2006
-- Description:
-- Constellation is one of important parts of OFDM communication systems. It takes
-- symbols as inputs and maps them to appropriate constellation points as dictated
-- by the modulation method specified. This process generates I and Q values (real
-- and imag values) which are then sent to IFFT for transformation. This file uses
-- 16QAM as modulation method and maps 4 bits inputs to 96,32,-33,-97 which present
-- constellation points.
-- Revision History:
-- v1.1, May.28.2006, change constellations positions to fit 802.11a
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;

-- ================================================================================

entity constellation is
	port
	(
		-- clock input
		clk: in std_logic;
		-- asynchroism clear input
		aclr: in std_logic;
		-- 4bit width input data ports
		inputData: in std_logic_vector (3 downto 0);
		-- Real and Imag output
		outputReal: out std_logic_vector (9 downto 0);
		outputImag: out std_logic_vector (9 downto 0);
		-- simple ALTERA Atlantic interface ports
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end constellation;

-- ================================================================================

architecture structure of constellation is

-- --------------------------------------------------------------------------------

-- signal declaration

-- interval data signals
signal real: std_logic_vector (9 downto 0);
signal imag: std_logic_vector (9 downto 0);

-- interval Atlantic interface signals
signal interval_sink_ena: std_logic;
signal interval_source_val: std_logic;
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

-- part1: generate output data

-- data replace process
process(clk,aclr,inputData)
begin
	if aclr = '1' then
		real <= "0000000000";
		imag <= "0000000000";
	else
		if rising_edge(clk) then
			if sink_val = '1' then
				case inputData is
					-- make 16 constellations using 96,32,-32,-97
					-- constellations position is following 802.11a
					-- for more details please search in 802.11a documents
					when "0010" =>
						real <= "1110011111"; -- -97
						imag <= "0001100000"; -- 96
					when "0110" =>
						real <= "1111011111"; -- -33
						imag <= "0001100000"; -- 96
					when "1110" =>
						real <= "0000100000"; -- 32
						imag <= "0001100000"; -- 96
					when "1010" =>
						real <= "0001100000"; -- 96
						imag <= "0001100000"; -- 96
					when "0011" =>
						real <= "1110011111"; -- -97
						imag <= "0000100000"; -- 32
					when "0111" =>
						real <= "1111011111"; -- -33
						imag <= "0000100000"; -- 32
					when "1111" =>
						real <= "0000100000"; -- 32
						imag <= "0000100000"; -- 32
					when "1011" =>
						real <= "0001100000"; -- 96
						imag <= "0000100000"; -- 32
					when "0001" =>
						real <= "1110011111"; -- -97
						imag <= "1111011111"; -- -33
					when "0101" =>
						real <= "1111011111"; -- -33
						imag <= "1111011111"; -- -33
					when "1101" =>
						real <= "0000100000"; -- 32
						imag <= "1111011111"; -- -33
					when "1001" =>
						real <= "0001100000"; -- 96
						imag <= "1111011111"; -- -33
					when "0000" =>
						real <= "1110011111"; -- -97
						imag <= "1110011111"; -- -97
					when "0100" =>
						real <= "1111011111"; -- -33
						imag <= "1110011111"; -- -97
					when "1100" =>
						real <= "0000100000"; -- 32
						imag <= "1110011111"; -- -97
					when "1000" =>
						real <= "0001100000"; -- 96
						imag <= "1110011111"; -- -97
					when others =>
						real <= "0000000000";
						imag <= "0000000000";
				end case;
			else
				real <= "0000000000";
				imag <= "0000000000";
			end if;
		end if;
	end if;
end process;

process(clk,real,imag)
begin
	if falling_edge(clk) then -- using falling edge
		outputReal <= real;
		outputImag <= imag;
	end if;
end process;

-- --------------------------------------------------------------------------------

-- part2: Atlantic interface outputs

-- generate interval_sink_ena
process(clk,aclr,source_ena)
begin
	if aclr = '1' then
		interval_sink_ena <= '0';
	else
		if rising_edge(clk) then
			interval_sink_ena <= source_ena;
		end if;
	end if;
end process;

-- output sink_ena
process(clk,interval_sink_ena)
begin
	if falling_edge(clk) then -- using falling edge
		sink_ena <= interval_sink_ena;
	end if;
end process;

-- generate and output source val sop eop
process(clk,sink_val,sink_sop,sink_eop)
begin
	if rising_edge(clk) then
		interval_source_val <= sink_val;
		interval_source_sop <= sink_sop;
		interval_source_eop <= sink_eop;
	end if;
end process;

process(clk,interval_source_val,interval_source_sop,interval_source_eop)
begin
	if falling_edge(clk) then -- using falling edge
		source_val <= interval_source_val;
		source_sop <= interval_source_sop;
		source_eop <= interval_source_eop;
	end if;
end process;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================================