rsdecoderbuffer.vhd

RS的编码。最新的移动多媒体应用技术的源代码

-- ================================================================================
-- File: RSdecoderbuffer.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.30.2006
-- Description:
-- RS decoder buffer is a buffer between DeIntereaver and RS decoder. It reads
-- datas from DeInterleaver and packet datas, at last sent to RS decoder.
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- ================================================================================

entity RSdecoderbuffer is
	port
	(
		-- clock input
		clk: in std_logic;
		-- asynchroism clear input
		aclr: in std_logic;
		-- 10 bit width input and output data ports
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		-- simple ALTERA Atlantic interface ports
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end RSdecoderbuffer;

-- ================================================================================

architecture structure of RSdecoderbuffer is

-- --------------------------------------------------------------------------------

-- declarations

-- fifo declaration
-- 128 words * 4 bits
component fifo_RSdecoderbuffer
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdreq		: IN STD_LOGIC ;
		wrreq		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
		usedw		: OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
	);
end component;
-- connection signals
signal outputFIFO: std_logic_vector (3 downto 0);
signal readEnaFIFO: std_logic;
signal usedwFIFO: std_logic_vector (6 downto 0);
signal usedwIntFIFO: natural range 0 to 128;
signal readAddFIFO: natural range 0 to 5;

-- indicate read fifo process
signal isRead: std_logic;

-- interval interface signals
signal interval_sink_ena: std_logic;
signal interval_source_val: std_logic;
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

-- fifo connection
u1: fifo_RSdecoderbuffer port map
	(
		aclr => aclr, clock => clk,
		data => inputData, wrreq => sink_val,
		q => outputFIFO, rdreq => readEnaFIFO,
		usedw => usedwFIFO
	);
	
-- convert to integer
usedwIntFIFO <= to_integer(unsigned(usedwFIFO));

-- sink_ena
process(aclr,clk,usedwIntFIFO)
begin
	if aclr = '1' then
		interval_sink_ena <= '0';
	else
		if rising_edge(clk) then
			if usedwIntFIFO <= 92 then -- 128 - 36 = 92
				interval_sink_ena <= '1';
			else
				interval_sink_ena <= '0';
			end if;
		end if;
	end if;
end process;

-- isRead
process(aclr,clk,usedwIntFIFO,readAddFIFO)
begin
	if aclr = '1' then
		isRead <= '0';
	else
		if rising_edge(clk) then
			if usedwIntFIFO >= 6 and readAddFIFO = 0 then
				isRead <= '1';
			elsif readAddFIFO = 4 then -- shut down eariler
				isRead <= '0';
			end if;
		end if;
	end if;
end process;

-- read ena
process(clk,isRead,source_ena)
begin
	if rising_edge(clk) then
		if isRead = '1' and source_ena = '1' then
			readEnaFIFO <= '1';
		else
			readEnaFIFO <= '0';
		end if;
	end if;
end process;

-- reading from FIFO process
process(aclr,clk,readEnaFIFO)
begin
	if aclr = '1' then
		readAddFIFO <= 0;
	else
		if rising_edge(clk) then
			if readEnaFIFO = '1' then
				if readAddFIFO = 5 then
					readAddFIFO <= 0;
				else
					readAddFIFO <= readAddFIFO + 1;
				end if;
			else
				readAddFIFO <= 0;
			end if;
		end if;
	end if;
end process;

-- generate interface signals
process(clk,readEnaFIFO,readAddFIFO)
begin
	if rising_edge(clk) then
		if readEnaFIFO = '1' then
			interval_source_val <= '1';
			if readAddFIFO = 0 then
				interval_source_sop <= '1';
				interval_source_eop <= '0';
			elsif readAddFIFO = 5 then
				interval_source_sop <= '0';
				interval_source_eop <= '1';
			else
				interval_source_sop <= '0';
				interval_source_eop <= '0';
			end if;
		else
			interval_source_val <= '0';
			interval_source_sop <= '0';
			interval_source_eop <= '0';
		end if;
	end if;
end process;

-- synchronize output using falling edge
process(clk,outputFIFO,interval_sink_ena,interval_source_val,
		interval_source_sop,interval_source_eop)
begin
	if falling_edge(clk) then -- using falling edge
		outputData <= outputFIFO;
		sink_ena <= interval_sink_ena;
		source_val <= interval_source_val;
		source_sop <= interval_source_sop;
		source_eop <= interval_source_eop;
	end if;
end process;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================================