stuff.vhd

RS的编码。最新的移动多媒体应用技术的源代码

-- ================================================================================
-- File: Stuff.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: 4.27.2006
-- Description:
-- This part named Stuff is designed for IFFT Core. Packets from Interleaver's 
-- output ports with 36 words length is not satified for 64 points FFT Core. Thus,
-- Zero Stuff adds another 28 zeros to enlarge packets up to 64 words long.
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

-- ================================================================================

entity Stuff is
	port
	(
		-- clock input
		clk: in std_logic;
		-- asynchroism clear input
		aclr: in std_logic;
		-- 4bit width input and output data ports
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		-- simple ALTERA Atlantic interface ports
		sink_ena: out std_logic;
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		source_ena: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic
	);
end Stuff;

-- ================================================================================

architecture structure of Stuff is

-- --------------------------------------------------------------------------------

-- declarations

-- 4bit * 64 words RAM
component ram_Stuff
	PORT
	(
		aclr		: IN STD_LOGIC  := '0';
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
	);
end component;

-- component connection signals
signal readAdd_ram: std_logic_vector (5 downto 0);
signal readEna_ram: std_logic;
signal writeAdd_ram: std_logic_vector (5 downto 0);
signal writeEna_ram: std_logic;
signal outputData_ram: std_logic_vector (3 downto 0);

-- write and read Address count Number.
signal writeAddNum: integer range 0 to 35;
signal readAddNum: integer range 0 to 63;

-- sink_eop delay 1 clk signal
signal sink_eop_d: std_logic;

-- read process flag signal
signal isRead: std_logic;

-- interval interface
signal interval_source_val: std_logic;
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;
signal interval_source_val_d: std_logic;
signal interval_source_sop_d: std_logic;
signal interval_source_eop_d: std_logic;
signal interval_sink_ena: std_logic;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

-- part1: ram connections part

-- ram connections
u1: ram_Stuff port map
	(
		aclr => aclr, clock => clk,
		data => inputData, q => outputData_ram,
		rdaddress => readAdd_ram, wraddress => writeAdd_ram,
		rden => readEna_ram, wren => writeEna_ram
	);

-- convert into std_logic_vector and connect	
writeAdd_ram <= conv_std_logic_vector(writeAddNum,6);
readAdd_ram <= conv_std_logic_vector(readAddNum,6);

-- synchronize output data using falling edge
process(clk,outputData_ram)
begin
	if falling_edge(clk) then -- using falling edge
		outputData <= outputData_ram;
	end if;
end process;

-- --------------------------------------------------------------------------------

-- part2: write process part

-- write into RAM process
writeEna_ram <= sink_val or sink_sop;

-- writeAddNum generator
process(clk,aclr,writeEna_ram)
begin
	if aclr = '1' then
		writeAddNum <= 0;
	else
		if falling_edge(clk) then -- using falling edge
			if sink_val = '1' then
				if writeAddNum = 35 then
					writeAddNum <= 0;
				else
					writeAddNum <= writeAddNum + 1;
				end if;
			else
				writeAddNum <= 0;
			end if;
		end if;
	end if;
end process;

-- --------------------------------------------------------------------------------

-- part3: read process part

-- delay sink_eop 1 clk
process(clk,sink_eop)
begin
	if rising_edge(clk) then
		sink_eop_d <= sink_eop;
	end if;
end process;

-- generate isRead indicated read process
process(clk,sink_eop_d,readAddNum)
begin
	if rising_edge(clk) then
		if sink_eop_d = '1' then
			isRead <= '1';
		end if;
		if readAddNum = 63 then
			isRead <= '0';
		end if;
	end if;
end process;

-- control read enable
process(clk,isRead,source_ena)
begin
	if falling_edge(clk) then
		if isRead = '1' then
			readEna_ram <= source_ena;
		else
			readEna_ram <= '0';
		end if;
	end if;
end process;

-- generate read address
process(clk,aclr,source_ena,readEna_ram)
begin
	if aclr = '1' then
		readAddNum <= 0;
	else
		if falling_edge(clk) then
			if readEna_ram = '1' then
				if source_ena = '1' then
					if readAddNum = 63 then
						readAddNum <= 0;
					else
						readAddNum <= readAddNum + 1;
					end if;
				end if;
			else
				readAddNum <= 0;
			end if;
		end if;
	end if;
end process;

-- --------------------------------------------------------------------------------

-- part4: simple Atlantic interface part

-- source_val
process(aclr,readEna_ram)
begin
	if aclr = '1' then
		interval_source_val <= '0';
	else
		interval_source_val <= readEna_ram;
	end if;
end process;

-- source_sop and eop
process(aclr,clk,readAddNum,readEna_ram)
begin
	if aclr = '1' then
		interval_source_sop <= '0';
		interval_source_eop <= '0';
	else
		if rising_edge(clk) then
			if readAddNum = 0 then
				interval_source_sop <= readEna_ram;
				interval_source_eop <= '0';
			elsif readAddNum = 63 then
				interval_source_sop <= '0';
				interval_source_eop <= '1';
			else
				interval_source_sop <= '0';
				interval_source_eop <= '0';
			end if;
		end if;
	end if;
end process;

-- sink_ena
process(aclr,clk,writeAddNum,readAddNum)
begin
	if aclr = '1' then
		interval_sink_ena <= '1';
	else
		if rising_edge(clk) then
			if readAddNum = 36 then
				interval_sink_ena <= '1';
			end if;
			if writeAddNum = 35 then -- deassert sink_ena earlier
				interval_sink_ena <= '0';
			end if;
		end if;
	end if;
end process;

-- synchronize signals using falling edge
process(clk,interval_source_val,interval_source_sop,interval_source_eop)
begin
	if falling_edge(clk) then -- using falling edge
		interval_source_val_d <= interval_source_val;
		interval_source_sop_d <= interval_source_sop;
		interval_source_eop_d <= interval_source_eop;
		source_val <= interval_source_val_d;
		source_sop <= interval_source_sop_d;
		source_eop <= interval_source_eop_d;
		sink_ena <= interval_sink_ena;
	end if;
end process;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================================