cpimag.vhd

RS的编码。最新的移动多媒体应用技术的源代码

-- ================================================================================
-- File: CPimag.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: 5.18.2006
-- Description:
-- CP means "Append Cyclic Prefix" that is an essential part of a OFDM system. For
-- my OFDM system, length of data packeg is 64 words. CP add another 1/4 packeg's
-- datas and enlarge to 80 words per packeg. CP part is following IFFT parts and
-- thus its interface signals change a little for IFFT. Output datas from IFFT
-- module contains real and imag parts. Therefore, two CPs for IFFT outputs are
-- needed.
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

-- ================================================================================

entity CPimag is
	port
	(
		-- clock input
		clk: in std_logic;
		-- asynchroism clear input
		aclr: in std_logic;
		-- 4bit width Data ports
		inputData: in std_logic_vector (9 downto 0);
		outputData: out std_logic_vector (9 downto 0);
		-- simple ALTERA Atlantic interface ports
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end CPimag;

-- ================================================================================

architecture structure of CPimag is

-- --------------------------------------------------------------------------------

-- component declaration
component ram_CPimag
	PORT
	(
		aclr		: IN STD_LOGIC  := '0';
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		rden		: IN STD_LOGIC  := '1';
		wraddress		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
	);
end component;
signal outputRAM: std_logic_vector (9 downto 0);
signal readEna: std_logic;
signal readAdd: std_logic_vector (5 downto 0);
signal readAddInt: integer range 0 to 63;
signal readCount: integer range 0 to 79;
signal writeAdd: std_logic_vector (5 downto 0);
signal writeAddInt: integer range 0 to 63;

-- signal declarations

-- synchronize input signals using Falling edge
signal inputData_f: std_logic_vector (9 downto 0);
signal sink_val_f: std_logic;
signal sink_sop_f: std_logic;
signal sink_eop_f: std_logic;

-- read (output) process start / end flag signal
signal isRead: std_logic;

-- interval interface signals
signal interval_source_sop: std_logic;
signal interval_source_eop: std_logic;

-- delayed signals
signal interval_source_val_d1: std_logic;
signal interval_source_val_d2: std_logic;
signal interval_source_sop_d1: std_logic;
signal interval_source_sop_d2: std_logic;
signal interval_source_eop_d1: std_logic;
signal interval_source_eop_d2: std_logic;
signal interval_source_eop_d3: std_logic;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

-- synchronize input signals using falling edge
process(clk,inputData,sink_val,sink_sop,sink_eop)
begin
	if falling_edge(clk) then
		inputData_f <= inputData;
		sink_val_f <= sink_val;
		sink_sop_f <= sink_sop;
		sink_eop_f <= sink_eop;
	end if;
end process;

-- RAM connetion
-- input data is writed into RAM directly
u1: ram_CPimag port map
	(
		clock => clk, aclr => aclr,
		data => inputData_f, q => outputRAM,
		rden => readEna, rdaddress => readAdd,
		wren => sink_val_f, wraddress => writeAdd
	);

-- convert integer to std_logic_vector
readAdd <= conv_std_logic_vector(readAddInt,6);
writeAdd <= conv_std_logic_vector(writeAddInt,6);

-- write address generator
process(aclr,clk,sink_val_f,sink_sop_f,sink_eop_f)
begin
	if aclr = '1' then
		writeAddInt <= 0;
	else
		if rising_edge(clk) then
			if sink_val_f = '1' or sink_sop_f = '1' then
				if writeAddInt = 63 then
					writeAddInt <= 0;
				else
					writeAddInt <= writeAddInt + 1;
				end if;
			elsif sink_eop_f = '1' then
				writeAddInt <= 0;
			else
				writeAddInt <= 0;
			end if;
		end if;
	end if;
end process;

-- flag signal controlling
process(clk,sink_eop_f,interval_source_eop)
begin
	if rising_edge(clk) then
		if sink_eop_f = '1' then
			isRead <= '1';
		elsif interval_source_eop = '1' then
			isRead <= '0';
		end if;
	end if;
end process;

-- RAM read enable
process(clk,isRead,source_ena)
begin
	if rising_edge(clk) then
		if isRead = '1' then
			readEna <= source_ena;
		else
			readEna <= '0';
		end if;
	end if;
end process;

-- read Count numbers that working when read enable = '1'
process(aclr,clk,readEna)
begin
	if aclr = '1' then
		readCount <= 0;
	else
		if rising_edge(clk) then
			if readEna = '1' then
				if readCount = 79 then
					readCount <= 0;
				else
					readCount <= readCount + 1;
				end if;
			end if;
		end if;
	end if;
end process;

-- change readCount into read address
process(readCount)
begin
	if readCount <= 15 then
		readAddInt <= readCount + 48;
	else
		readAddInt <= readCount - 16;
	end if;
end process;

-- generate source sop eop
process(readEna,readCount)
begin
	if readEna = '1' then
		if readCount = 78 then -- assert eop before Count = 79
			interval_source_sop <= '0';
			interval_source_eop <= '1';
		elsif readCount = 0 then
			interval_source_sop <= '1';
			interval_source_eop <= '0';
		else
			interval_source_sop <= '0';
			interval_source_eop <= '0';
		end if;
	else
		interval_source_sop <= '0';
		interval_source_eop <= '0';
	end if;
end process;

-- delay output interface signals
process(clk,readEna,interval_source_sop,interval_source_eop)
begin
	if rising_edge(clk) then
		interval_source_val_d1 <= readEna;
		interval_source_val_d2 <= interval_source_val_d1;
		interval_source_sop_d1 <= interval_source_sop;
		interval_source_sop_d2 <= interval_source_sop_d1;
		interval_source_eop_d1 <= interval_source_eop;
		interval_source_eop_d2 <= interval_source_eop_d1;
		interval_source_eop_d3 <= interval_source_eop_d2;
	end if;
end process;

-- synchronize output signals using falling edge
process(clk,outputRAM,interval_source_val_d2,
		interval_source_sop_d2,interval_source_eop_d3)
begin
	if falling_edge(clk) then
		outputData <= outputRAM;
		source_val <= interval_source_val_d2;
		source_sop <= interval_source_sop_d2;
		source_eop <= interval_source_eop_d3;
	end if;
end process;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================================