ofdm.vhd

RS的编码。最新的移动多媒体应用技术的源代码

-- ================================================================================
-- File: ofdm.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: 4.26.2006
-- Description:
-- Top level file of ofdm project which describe the interval connection mainly.
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

-- ================================================================================

entity ofdm is
	port
	(
		clock: in std_logic;
		reset: in std_logic;
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end ofdm;

-- ================================================================================

architecture connection of ofdm is

-- --------------------------------------------------------------------------------

-- component declaration

-- Reed-Solomon encoder generated by ALTERA ip toolbench
component RSencoder
	PORT (
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		rsin	: IN STD_LOGIC_VECTOR (4 DOWNTO 1);
		sink_val	: IN STD_LOGIC;
		sink_sop	: IN STD_LOGIC;
		sink_eop	: IN STD_LOGIC;
		source_ena	: IN STD_LOGIC;
		rsout	: OUT STD_LOGIC_VECTOR (4 DOWNTO 1);
		sink_ena	: OUT STD_LOGIC;
		source_val	: OUT STD_LOGIC;
		source_sop	: OUT STD_LOGIC;
		source_eop	: OUT STD_LOGIC
	);
end component;
signal rsout_RSencoder: std_logic_vector (3 downto 0);
signal source_ena_RSencoder: std_logic;
signal source_val_RSencoder: std_logic;
signal source_sop_RSencoder: std_logic;
signal source_eop_RSencoder: std_logic;

-- R-S encoder output buffer
component RSbuffer
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		sink_val: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputData_RSbuffer: std_logic_vector (3 downto 0);
signal source_ena_RSbuffer: std_logic;
signal source_val_RSbuffer: std_logic;
signal source_sop_RSbuffer: std_logic;
signal source_eop_RSbuffer: std_logic;

-- Interleaver
component Interleaver
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputData_Interleaver: std_logic_vector (3 downto 0);
signal source_ena_Interleaver: std_logic;
signal source_val_Interleaver: std_logic;
signal source_sop_Interleaver: std_logic;
signal source_eop_Interleaver: std_logic;

-- Zero Stuff
component Stuff
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (3 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputData_Stuff: std_logic_vector (3 downto 0);
signal source_ena_Stuff: std_logic;
signal source_val_Stuff: std_logic;
signal source_sop_Stuff: std_logic;
signal source_eop_Stuff: std_logic;

-- Constellation
component Constellation
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (3 downto 0);
		outputReal: out std_logic_vector (9 downto 0);
		outputImag: out std_logic_vector (9 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		sink_ena: out std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputReal_Constellation: std_logic_vector (9 downto 0);
signal outputImag_Constellation: std_logic_vector (9 downto 0);
signal source_ena_Constellation: std_logic;
signal source_sop_Constellation: std_logic;

-- IFFT core generated by ALTERA IP toolbench
component IFFTcore
	PORT (
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		master_sink_dav	: IN STD_LOGIC;
		master_sink_sop	: IN STD_LOGIC;
		master_source_dav	: IN STD_LOGIC;
		inv_i	: IN STD_LOGIC;
		data_real_in	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		data_imag_in	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		fft_real_out	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		fft_imag_out	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		exponent_out	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
		master_sink_ena	: OUT STD_LOGIC;
		master_source_sop	: OUT STD_LOGIC;
		master_source_eop	: OUT STD_LOGIC;
		master_source_ena	: OUT STD_LOGIC
	);
end component;
signal outputReal_IFFT: std_logic_vector (9 downto 0);
signal outputImag_IFFT: std_logic_vector (9 downto 0);
signal source_val_IFFT: std_logic;
signal source_sop_IFFT: std_logic;
signal source_eop_IFFT: std_logic;

-- Append Cyclic Prefix Real part
component CPreal
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (9 downto 0);
		outputData: out std_logic_vector (9 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputReal_CP: std_logic_vector (9 downto 0);
signal source_val_CP: std_logic;

-- Append Cyclic Prefix imag part
component CPimag
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (9 downto 0);
		outputData: out std_logic_vector (9 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputImag_CP: std_logic_vector (9 downto 0);

-- Cyclic Prefix Remover Real
component CPRemoveReal
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (9 downto 0);
		outputData: out std_logic_vector (9 downto 0);
		sink_val: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputReal_CPR: std_logic_vector (9 downto 0);
signal source_ena_CPR: std_logic;
signal source_sop_CPR: std_logic;

-- Cyclic Prefix Remover Imag
component CPRemoveImag
	port
	(
		clk: in std_logic;
		aclr: in std_logic;
		inputData: in std_logic_vector (9 downto 0);
		outputData: out std_logic_vector (9 downto 0);
		sink_val: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic;
		source_ena: in std_logic
	);
end component;
signal outputImag_CPR: std_logic_vector (9 downto 0);

-- FFT in receiver
component FFTcore
	PORT (
		clk	: IN STD_LOGIC;
		reset	: IN STD_LOGIC;
		master_sink_dav	: IN STD_LOGIC;
		master_sink_sop	: IN STD_LOGIC;
		master_source_dav	: IN STD_LOGIC;
		inv_i	: IN STD_LOGIC;
		data_real_in	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		data_imag_in	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
		fft_real_out	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		fft_imag_out	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		exponent_out	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
		master_sink_ena	: OUT STD_LOGIC;
		master_source_sop	: OUT STD_LOGIC;
		master_source_eop	: OUT STD_LOGIC;
		master_source_ena	: OUT STD_LOGIC
	);
end component;
signal outputReal_FFT: std_logic_vector (9 downto 0);
signal outputImag_FFT: std_logic_vector (9 downto 0);
signal source_val_FFT: std_logic;
signal source_sop_FFT: std_logic;
signal source_eop_FFT: std_logic;

-- FFT scaler
component FFTscale
	port
	(
		clk: in std_logic;
		inputReal: in std_logic_vector (9 downto 0);
		inputImag: in std_logic_vector (9 downto 0);
		outputReal: out std_logic_vector (9 downto 0);
		outputImag: out std_logic_vector (9 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic
	);
end component;
signal outputReal_FFTscale: std_logic_vector (9 downto 0);
signal outputImag_FFTscale: std_logic_vector (9 downto 0);
signal source_val_FFTscale: std_logic;
signal source_sop_FFTscale: std_logic;
signal source_eop_FFTscale: std_logic;

-- De-constellation
component DeConstellation
	port
	(
		clk: in std_logic;
		inputReal: in std_logic_vector (9 downto 0);
		inputImag: in std_logic_vector (9 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic
	);
end component;
signal outputData_DeConstellation: std_logic_vector (3 downto 0);
signal source_val_DeConstellation: std_logic;