fifo_cpremovereal.vhd

RS的编码。最新的移动多媒体应用技术的源代码

-- megafunction wizard: %FIFO%CBX%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: scfifo 

-- ============================================================
-- File Name: fifo_CPRemoveReal.vhd
-- Megafunction Name(s):
-- 			scfifo
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
-- ************************************************************


--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions 
--and other software and tools, and its AMPP partner logic 
--functions, and any output files any of the foregoing 
--(including device programming or simulation files), and any 
--associated documentation or information are expressly subject 
--to the terms and conditions of the Altera Program License 
--Subscription Agreement, Altera MegaCore Function License 
--Agreement, or other applicable license agreement, including, 
--without limitation, that your use is for the sole purpose of 
--programming logic devices manufactured by Altera and sold by 
--Altera or its authorized distributors.  Please refer to the 
--applicable agreement for further details.


--scfifo ADD_RAM_OUTPUT_REGISTER="OFF" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" lpm_width=10 lpm_widthu=8 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr clock data q rdreq usedw wrreq
--VERSION_BEGIN 5.1 cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_fifo_common 2005:07:21:10:40:24:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_scfifo 2005:09:06:13:25:24:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ  VERSION_END


--a_dpfifo ADD_RAM_OUTPUT_REGISTER="OFF" ALLOW_RWCYCLE_WHEN_FULL="OFF" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=256 LPM_SHOWAHEAD="OFF" lpm_width=10 lpm_widthu=8 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock data q rreq sclr usedw wreq
--VERSION_BEGIN 5.1 cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:11:08:14:10:50:SJ cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_fifo_common 2005:07:21:10:40:24:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_lpm_mux 2005:12:13:16:24:06:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_scfifo 2005:09:06:13:25:24:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ cbx_util_mgl 2005:09:12:10:23:22:SJ  VERSION_END


--a_fefifo ALLOW_RWCYCLE_WHEN_FULL="OFF" LPM_NUMWORDS=256 lpm_widthad=8 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" aclr clock rreq sclr usedw_out wreq
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_fifo_common 2005:07:21:10:40:24:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ  VERSION_END


--lpm_counter DEVICE_FAMILY="Cyclone" lpm_width=8 aclr clock cnt_en q sclr updown
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:12:13:10:36:54:SJ cbx_lpm_add_sub 2005:11:02:10:42:42:SJ cbx_lpm_compare 2005:07:11:09:41:28:SJ cbx_lpm_counter 2005:08:23:15:49:38:SJ cbx_lpm_decode 2005:04:27:14:28:48:SJ cbx_mgl 2006:01:12:16:15:18:SJ cbx_stratix 2005:12:28:11:18:26:SJ cbx_stratixii 2005:11:02:10:43:56:SJ  VERSION_END

 LIBRARY cyclone;
 USE cyclone.all;

--synthesis_resources = lut 8 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;

 ENTITY  fifo_CPRemoveReal_cntr_bc7 IS 
	 PORT 
	 ( 
		 aclr	:	IN  STD_LOGIC := '0';
		 clock	:	IN  STD_LOGIC;
		 cnt_en	:	IN  STD_LOGIC := '1';
		 q	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0);
		 sclr	:	IN  STD_LOGIC := '0';
		 updown	:	IN  STD_LOGIC := '1'
	 ); 
 END fifo_CPRemoveReal_cntr_bc7;

 ARCHITECTURE RTL OF fifo_CPRemoveReal_cntr_bc7 IS

	 ATTRIBUTE synthesis_clearbox : boolean;
	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
	 SIGNAL  wire_vcc	:	STD_LOGIC;
	 SIGNAL  wire_counter_cella_aload	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_counter_cella_0cout	:	STD_LOGIC;
	 SIGNAL  wire_counter_cella_1cout	:	STD_LOGIC;
	 SIGNAL  wire_counter_cella_2cout	:	STD_LOGIC;
	 SIGNAL  wire_counter_cella_3cout	:	STD_LOGIC;
	 SIGNAL  wire_counter_cella_4cout	:	STD_LOGIC;
	 SIGNAL  wire_counter_cella_5cout	:	STD_LOGIC;
	 SIGNAL  wire_counter_cella_6cout	:	STD_LOGIC;
	 SIGNAL  wire_counter_cella_dataa	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_counter_cella_datac	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_counter_cella_ena	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_counter_cella_regout	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_counter_cella_sload	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_count_usedw_w_lg_w_lg_sset103w104w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_count_usedw_w_lg_clk_en111w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_count_usedw_w_lg_sset105w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_count_usedw_w_lg_sset103w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_count_usedw_w_lg_w_lg_sset105w106w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  wire_count_usedw_w_lg_w_lg_w_lg_cnt_en108w109w110w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_count_usedw_w_lg_w_lg_cnt_en108w109w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_count_usedw_w_lg_cnt_en108w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  wire_count_usedw_w_lg_sset107w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
	 SIGNAL  aclr_actual :	STD_LOGIC;
	 SIGNAL  clk_en	:	STD_LOGIC;
	 SIGNAL  data	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  s_val :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  safe_q :	STD_LOGIC_VECTOR (7 DOWNTO 0);
	 SIGNAL  sload	:	STD_LOGIC;
	 SIGNAL  sset	:	STD_LOGIC;
	 SIGNAL  updownDir :	STD_LOGIC;
	 COMPONENT  cyclone_lcell
	 GENERIC 
	 (
		cin_used	:	STRING := "false";
		lut_mask	:	STRING;
		operation_mode	:	STRING := "normal";
		output_mode	:	STRING := "reg_and_comb";
		register_cascade_mode	:	STRING := "off";
		sum_lutc_input	:	STRING := "datac";
		synch_mode	:	STRING := "off";
		lpm_type	:	STRING := "cyclone_lcell"
	 );
	 PORT
	 ( 
		aclr	:	IN STD_LOGIC := '0';
		aload	:	IN STD_LOGIC := '0';
		cin	:	IN STD_LOGIC := '0';
		clk	:	IN STD_LOGIC := '0';
		combout	:	OUT STD_LOGIC;
		cout	:	OUT STD_LOGIC;
		dataa	:	IN STD_LOGIC := '1';
		datab	:	IN STD_LOGIC := '1';
		datac	:	IN STD_LOGIC := '1';
		datad	:	IN STD_LOGIC := '1';
		ena	:	IN STD_LOGIC := '1';
		inverta	:	IN STD_LOGIC := '0';
		regcascin	:	IN STD_LOGIC := '0';
		regout	:	OUT STD_LOGIC;
		sclr	:	IN STD_LOGIC := '0';
		sload	:	IN STD_LOGIC := '0'
	 ); 
	 END COMPONENT;
 BEGIN

	wire_vcc <= '1';
	loop0 : FOR i IN 0 TO 7 GENERATE 
		wire_count_usedw_w_lg_w_lg_sset103w104w(i) <= wire_count_usedw_w_lg_sset103w(0) AND data(i);
	END GENERATE loop0;
	wire_count_usedw_w_lg_clk_en111w(0) <= clk_en AND wire_count_usedw_w_lg_w_lg_w_lg_cnt_en108w109w110w(0);
	loop2 : FOR i IN 0 TO 7 GENERATE 
		wire_count_usedw_w_lg_sset105w(i) <= sset AND s_val(i);
	END GENERATE loop2;
	wire_count_usedw_w_lg_sset103w(0) <= NOT sset;
	loop3 : FOR i IN 0 TO 7 GENERATE 
		wire_count_usedw_w_lg_w_lg_sset105w106w(i) <= wire_count_usedw_w_lg_sset105w(i) OR wire_count_usedw_w_lg_w_lg_sset103w104w(i);
	END GENERATE loop3;
	wire_count_usedw_w_lg_w_lg_w_lg_cnt_en108w109w110w(0) <= wire_count_usedw_w_lg_w_lg_cnt_en108w109w(0) OR sload;
	wire_count_usedw_w_lg_w_lg_cnt_en108w109w(0) <= wire_count_usedw_w_lg_cnt_en108w(0) OR sset;
	wire_count_usedw_w_lg_cnt_en108w(0) <= cnt_en OR sclr;
	wire_count_usedw_w_lg_sset107w(0) <= sset OR sload;
	aclr_actual <= aclr;
	clk_en <= '1';
	data <= (OTHERS => '0');
	q <= safe_q;
	s_val <= "11111111";
	safe_q <= wire_counter_cella_regout;
	sload <= '0';
	sset <= '0';
	updownDir <= updown;
	wire_counter_cella_aload <= "00000000";
	wire_counter_cella_dataa <= safe_q;
	wire_counter_cella_datac <= wire_count_usedw_w_lg_w_lg_sset105w106w;
	loop8 : FOR i IN 0 TO 7 GENERATE
		wire_counter_cella_ena(i) <= wire_count_usedw_w_lg_clk_en111w(0);
	END GENERATE loop8;
	loop9 : FOR i IN 0 TO 7 GENERATE
		wire_counter_cella_sload(i) <= wire_count_usedw_w_lg_sset107w(0);
	END GENERATE loop9;
	counter_cella_0 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "false",
		lut_mask => "5599",
		operation_mode => "arithmetic",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(0),
		clk => clock,
		cout => wire_counter_cella_0cout,
		dataa => wire_counter_cella_dataa(0),
		datab => updownDir,
		datac => wire_counter_cella_datac(0),
		ena => wire_counter_cella_ena(0),
		regout => wire_counter_cella_regout(0),
		sclr => sclr,
		sload => wire_counter_cella_sload(0)
	  );
	counter_cella_1 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "true",
		lut_mask => "5A90",
		operation_mode => "arithmetic",
		sum_lutc_input => "cin",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(1),
		cin => wire_counter_cella_0cout,
		clk => clock,
		cout => wire_counter_cella_1cout,
		dataa => wire_counter_cella_dataa(1),
		datab => updownDir,
		datac => wire_counter_cella_datac(1),
		ena => wire_counter_cella_ena(1),
		regout => wire_counter_cella_regout(1),
		sclr => sclr,
		sload => wire_counter_cella_sload(1)
	  );
	counter_cella_2 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "true",
		lut_mask => "5A90",
		operation_mode => "arithmetic",
		sum_lutc_input => "cin",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(2),
		cin => wire_counter_cella_1cout,
		clk => clock,
		cout => wire_counter_cella_2cout,
		dataa => wire_counter_cella_dataa(2),
		datab => updownDir,
		datac => wire_counter_cella_datac(2),
		ena => wire_counter_cella_ena(2),
		regout => wire_counter_cella_regout(2),
		sclr => sclr,
		sload => wire_counter_cella_sload(2)
	  );
	counter_cella_3 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "true",
		lut_mask => "5A90",
		operation_mode => "arithmetic",
		sum_lutc_input => "cin",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(3),
		cin => wire_counter_cella_2cout,
		clk => clock,
		cout => wire_counter_cella_3cout,
		dataa => wire_counter_cella_dataa(3),
		datab => updownDir,
		datac => wire_counter_cella_datac(3),
		ena => wire_counter_cella_ena(3),
		regout => wire_counter_cella_regout(3),
		sclr => sclr,
		sload => wire_counter_cella_sload(3)
	  );
	counter_cella_4 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "true",
		lut_mask => "5A90",
		operation_mode => "arithmetic",
		sum_lutc_input => "cin",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(4),
		cin => wire_counter_cella_3cout,
		clk => clock,
		cout => wire_counter_cella_4cout,
		dataa => wire_counter_cella_dataa(4),
		datab => updownDir,
		datac => wire_counter_cella_datac(4),
		ena => wire_counter_cella_ena(4),
		regout => wire_counter_cella_regout(4),
		sclr => sclr,
		sload => wire_counter_cella_sload(4)
	  );
	counter_cella_5 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "true",
		lut_mask => "5A90",
		operation_mode => "arithmetic",
		sum_lutc_input => "cin",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(5),
		cin => wire_counter_cella_4cout,
		clk => clock,
		cout => wire_counter_cella_5cout,
		dataa => wire_counter_cella_dataa(5),
		datab => updownDir,
		datac => wire_counter_cella_datac(5),
		ena => wire_counter_cella_ena(5),
		regout => wire_counter_cella_regout(5),
		sclr => sclr,
		sload => wire_counter_cella_sload(5)
	  );
	counter_cella_6 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "true",
		lut_mask => "5A90",
		operation_mode => "arithmetic",
		sum_lutc_input => "cin",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(6),
		cin => wire_counter_cella_5cout,
		clk => clock,
		cout => wire_counter_cella_6cout,
		dataa => wire_counter_cella_dataa(6),
		datab => updownDir,
		datac => wire_counter_cella_datac(6),
		ena => wire_counter_cella_ena(6),
		regout => wire_counter_cella_regout(6),
		sclr => sclr,
		sload => wire_counter_cella_sload(6)
	  );
	counter_cella_7 :  cyclone_lcell
	  GENERIC MAP (
		cin_used => "true",
		lut_mask => "5A90",
		operation_mode => "normal",
		sum_lutc_input => "cin",
		synch_mode => "on"
	  )
	  PORT MAP ( 
		aclr => aclr_actual,
		aload => wire_counter_cella_aload(7),
		cin => wire_counter_cella_6cout,
		clk => clock,
		dataa => wire_counter_cella_dataa(7),
		datab => updownDir,
		datac => wire_counter_cella_datac(7),
		datad => wire_vcc,
		ena => wire_counter_cella_ena(7),
		regout => wire_counter_cella_regout(7),
		sclr => sclr,
		sload => wire_counter_cella_sload(7)
	  );

 END RTL; --fifo_CPRemoveReal_cntr_bc7

--synthesis_resources = lut 10 
 LIBRARY ieee;
 USE ieee.std_logic_1164.all;