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📄 ram_cpremoveimag.vhd

📁 RS的编码。最新的移动多媒体应用技术的源代码
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123 
		PORT_B_ADDRESS_WIDTH => 7,
		PORT_B_DATA_OUT_CLEAR => "clear0",
		PORT_B_DATA_OUT_CLOCK => "clock1",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 1,
		PORT_B_LAST_ADDRESS => 79,
		PORT_B_LOGICAL_RAM_DEPTH => 80,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		POWER_UP_UNINITIALIZED => "false",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock0,
		clr0 => aclr0,
		ena0 => wren_a,
		portaaddr => wire_ram_block1a_1portaaddr,
		portadatain => wire_ram_block1a_1portadatain,
		portawe => wire_ram_block1a_portawe(1),
		portbaddr => wire_ram_block1a_1portbaddr,
		portbdataout => wire_ram_block1a_1portbdataout,
		portbrewe => rden_b
	  );
	ram_block1a_2 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "clear0",
		PORT_A_ADDRESS_WIDTH => 7,
		PORT_A_DATA_IN_CLEAR => "clear0",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 2,
		PORT_A_LAST_ADDRESS => 79,
		PORT_A_LOGICAL_RAM_DEPTH => 80,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_ADDRESS_CLEAR => "clear0",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 7,
		PORT_B_DATA_OUT_CLEAR => "clear0",
		PORT_B_DATA_OUT_CLOCK => "clock1",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 2,
		PORT_B_LAST_ADDRESS => 79,
		PORT_B_LOGICAL_RAM_DEPTH => 80,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		POWER_UP_UNINITIALIZED => "false",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock0,
		clr0 => aclr0,
		ena0 => wren_a,
		portaaddr => wire_ram_block1a_2portaaddr,
		portadatain => wire_ram_block1a_2portadatain,
		portawe => wire_ram_block1a_portawe(2),
		portbaddr => wire_ram_block1a_2portbaddr,
		portbdataout => wire_ram_block1a_2portbdataout,
		portbrewe => rden_b
	  );
	ram_block1a_3 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "clear0",
		PORT_A_ADDRESS_WIDTH => 7,
		PORT_A_DATA_IN_CLEAR => "clear0",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 3,
		PORT_A_LAST_ADDRESS => 79,
		PORT_A_LOGICAL_RAM_DEPTH => 80,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_ADDRESS_CLEAR => "clear0",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 7,
		PORT_B_DATA_OUT_CLEAR => "clear0",
		PORT_B_DATA_OUT_CLOCK => "clock1",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 3,
		PORT_B_LAST_ADDRESS => 79,
		PORT_B_LOGICAL_RAM_DEPTH => 80,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		POWER_UP_UNINITIALIZED => "false",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock0,
		clr0 => aclr0,
		ena0 => wren_a,
		portaaddr => wire_ram_block1a_3portaaddr,
		portadatain => wire_ram_block1a_3portadatain,
		portawe => wire_ram_block1a_portawe(3),
		portbaddr => wire_ram_block1a_3portbaddr,
		portbdataout => wire_ram_block1a_3portbdataout,
		portbrewe => rden_b
	  );
	ram_block1a_4 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "clear0",
		PORT_A_ADDRESS_WIDTH => 7,
		PORT_A_DATA_IN_CLEAR => "clear0",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 4,
		PORT_A_LAST_ADDRESS => 79,
		PORT_A_LOGICAL_RAM_DEPTH => 80,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_ADDRESS_CLEAR => "clear0",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 7,
		PORT_B_DATA_OUT_CLEAR => "clear0",
		PORT_B_DATA_OUT_CLOCK => "clock1",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 4,
		PORT_B_LAST_ADDRESS => 79,
		PORT_B_LOGICAL_RAM_DEPTH => 80,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		POWER_UP_UNINITIALIZED => "false",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock0,
		clr0 => aclr0,
		ena0 => wren_a,
		portaaddr => wire_ram_block1a_4portaaddr,
		portadatain => wire_ram_block1a_4portadatain,
		portawe => wire_ram_block1a_portawe(4),
		portbaddr => wire_ram_block1a_4portbaddr,
		portbdataout => wire_ram_block1a_4portbdataout,
		portbrewe => rden_b
	  );
	ram_block1a_5 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "clear0",
		PORT_A_ADDRESS_WIDTH => 7,
		PORT_A_DATA_IN_CLEAR => "clear0",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 5,
		PORT_A_LAST_ADDRESS => 79,
		PORT_A_LOGICAL_RAM_DEPTH => 80,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_ADDRESS_CLEAR => "clear0",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 7,
		PORT_B_DATA_OUT_CLEAR => "clear0",
		PORT_B_DATA_OUT_CLOCK => "clock1",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 5,
		PORT_B_LAST_ADDRESS => 79,
		PORT_B_LOGICAL_RAM_DEPTH => 80,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		POWER_UP_UNINITIALIZED => "false",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock0,
		clr0 => aclr0,
		ena0 => wren_a,
		portaaddr => wire_ram_block1a_5portaaddr,
		portadatain => wire_ram_block1a_5portadatain,
		portawe => wire_ram_block1a_portawe(5),
		portbaddr => wire_ram_block1a_5portbaddr,
		portbdataout => wire_ram_block1a_5portbdataout,
		portbrewe => rden_b
	  );
	ram_block1a_6 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "clear0",
		PORT_A_ADDRESS_WIDTH => 7,
		PORT_A_DATA_IN_CLEAR => "clear0",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 6,
		PORT_A_LAST_ADDRESS => 79,
		PORT_A_LOGICAL_RAM_DEPTH => 80,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_ADDRESS_CLEAR => "clear0",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 7,
		PORT_B_DATA_OUT_CLEAR => "clear0",
		PORT_B_DATA_OUT_CLOCK => "clock1",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 6,
		PORT_B_LAST_ADDRESS => 79,
		PORT_B_LOGICAL_RAM_DEPTH => 80,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK => "clock1",
		POWER_UP_UNINITIALIZED => "false",
		RAM_BLOCK_TYPE => "auto"
	  )
	  PORT MAP ( 
		clk0 => clock0,
		clk1 => clock0,
		clr0 => aclr0,
		ena0 => wren_a,
		portaaddr => wire_ram_block1a_6portaaddr,
		portadatain => wire_ram_block1a_6portadatain,
		portawe => wire_ram_block1a_portawe(6),
		portbaddr => wire_ram_block1a_6portbaddr,
		portbdataout => wire_ram_block1a_6portbdataout,
		portbrewe => rden_b
	  );
	ram_block1a_7 :  cyclone_ram_block
	  GENERIC MAP (
		CONNECTIVITY_CHECKING => "OFF",
		LOGICAL_RAM_NAME => "ALTSYNCRAM",
		MIXED_PORT_FEED_THROUGH_MODE => "dont_care",
		OPERATION_MODE => "dual_port",
		PORT_A_ADDRESS_CLEAR => "clear0",
		PORT_A_ADDRESS_WIDTH => 7,
		PORT_A_DATA_IN_CLEAR => "clear0",
		PORT_A_DATA_WIDTH => 1,
		PORT_A_FIRST_ADDRESS => 0,
		PORT_A_FIRST_BIT_NUMBER => 7,
		PORT_A_LAST_ADDRESS => 79,
		PORT_A_LOGICAL_RAM_DEPTH => 80,
		PORT_A_LOGICAL_RAM_WIDTH => 10,
		PORT_A_WRITE_ENABLE_CLEAR => "clear0",
		PORT_B_ADDRESS_CLEAR => "clear0",
		PORT_B_ADDRESS_CLOCK => "clock1",
		PORT_B_ADDRESS_WIDTH => 7,
		PORT_B_DATA_OUT_CLEAR => "clear0",
		PORT_B_DATA_OUT_CLOCK => "clock1",
		PORT_B_DATA_WIDTH => 1,
		PORT_B_FIRST_ADDRESS => 0,
		PORT_B_FIRST_BIT_NUMBER => 7,
		PORT_B_LAST_ADDRESS => 79,
		PORT_B_LOGICAL_RAM_DEPTH => 80,
		PORT_B_LOGICAL_RAM_WIDTH => 10,
		PORT_B_READ_ENABLE_WRITE_ENABLE_CLEAR => "clear0",
123

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