deconstellation.vhd

RS的编码。最新的移动多媒体应用技术的源代码

-- ================================================================================
-- File: DeConstellation.vhd
-- Version: v1.0
-- Author: olivercamel
-- Date: May.27.2006
-- Description:
-- De-constellation is used to change constellations into datas. Constellation's
-- position is following 802.11a's documents. For more informations, read
-- Constellation.vhd as well.
-- ================================================================================

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- ================================================================================

entity DeConstellation is
	port
	(
		-- clock input
		clk: in std_logic;
		-- 10 bits width input and output data ports
		inputReal: in std_logic_vector (9 downto 0);
		inputImag: in std_logic_vector (9 downto 0);
		outputData: out std_logic_vector (3 downto 0);
		-- simple ALTERA Atlantic interface ports
		sink_val: in std_logic;
		sink_sop: in std_logic;
		sink_eop: in std_logic;
		source_val: out std_logic;
		source_sop: out std_logic;
		source_eop: out std_logic
	);
end DeConstellation;

-- ================================================================================

architecture structure of DeConstellation is

-- --------------------------------------------------------------------------------

-- signal declarations

-- synchronizaiton signals using falling edge.
signal outputData_f: std_logic_vector (3 downto 0);
signal source_val_f: std_logic;
signal source_sop_f: std_logic;
signal source_eop_f: std_logic;

-- --------------------------------------------------------------------------------

begin

-- --------------------------------------------------------------------------------

process(clk,sink_val,sink_sop,sink_eop,inputReal,inputImag)
begin
	if rising_edge(clk) then
		if sink_val = '1' then
			if signed(inputReal) >= -128 and signed(inputReal) <= -64 then
				if signed(inputImag) >= -128 and signed(inputImag) <= -64 then
					outputData_f <= "0000";
				elsif signed(inputImag) > -64 and signed(inputImag) <= 0 then
					outputData_f <= "0001";
				elsif signed(inputImag) > 0 and signed(inputImag) <= 64 then
					outputData_f <= "0011";
				elsif signed(inputImag) > 64 and signed(inputImag) <= 128 then
					outputData_f <= "0010";
				else -- error
					outputData_f <= "0000";
				end if;
			elsif signed(inputReal) > -64 and signed(inputReal) <= 0 then
				if signed(inputImag) >= -128 and signed(inputImag) <= -64 then
					outputData_f <= "0100";
				elsif signed(inputImag) > -64 and signed(inputImag) <= 0 then
					outputData_f <= "0101";
				elsif signed(inputImag) > 0 and signed(inputImag) <= 64 then
					outputData_f <= "0111";
				elsif signed(inputImag) > 64 and signed(inputImag) <= 128 then
					outputData_f <= "0110";
				else
					outputData_f <= "0000";
				end if;
			elsif signed(inputReal) > 0 and signed(inputReal) <= 64 then
				if signed(inputImag) >= -128 and signed(inputImag) <= -64 then
					outputData_f <= "1100";
				elsif signed(inputImag) > -64 and signed(inputImag) <= 0 then
					outputData_f <= "1101";
				elsif signed(inputImag) > 0 and signed(inputImag) <= 64 then
					outputData_f <= "1111";
				elsif signed(inputImag) > 64 and signed(inputImag) <= 128 then
					outputData_f <= "1110";
				else
					outputData_f <= "0000";
				end if;
			elsif signed(inputReal) > 64 and signed(inputReal) <= 128 then
				if signed(inputImag) >= -128 and signed(inputImag) <= -64 then
					outputData_f <= "1000";
				elsif signed(inputImag) > -64 and signed(inputImag) <= 0 then
					outputData_f <= "1001";
				elsif signed(inputImag) > 0 and signed(inputImag) <= 64 then
					outputData_f <= "1011";
				elsif signed(inputImag) > 64 and signed(inputImag) <= 128 then
					outputData_f <= "1010";
				else
					outputData_f <= "0000";
				end if;
			else
				outputData_f <= "0000";
			end if;
			source_val_f <= '1';
			source_sop_f <= sink_sop;
			source_eop_f <= sink_eop;
		else
			outputData_f <= "0000";
			source_val_f <= '0';
			source_sop_f <= '0';
			source_eop_f <= '0';
		end if;
	end if;
end process;

process(clk,outputData_f,source_val_f,source_sop_f,source_eop_f)
begin
	if falling_edge(clk) then
		outputData <= outputData_f;
		source_val <= source_val_f;
		source_sop <= source_sop_f;
		source_eop <= source_eop_f;
	end if;
end process;

-- --------------------------------------------------------------------------------

end structure;

-- ================================================================================