lan91c111_adapter.h

嵌入式网络芯片lan91c111的wince源码。

 /*
 *
 *    Copyright (c) Standard MicroSystems Corporation.  All Rights Reserved.
 *
 *				    LAN91C111 Driver for Windows CE .NET
 *
 *							 Revision History
 *_______________________________________________________________________________
 *     Author		  Date		Version		Description
 *_______________________________________________________________________________
 * Pramod Bhardwaj  6/18/2002	  0.1		Beta Release 
 * Pramod Bhardwaj	7/15/2002	  1.0       Release 
 *_______________________________________________________________________________
 *
 *Description
 *              Hardware specific and driver datastructure declarations
 *
 */
#ifndef __LAN91C111_ADAPTER__
#define __LAN91C111_ADAPTER__

//Windows CE debug zones
#define ZONE_ERROR      DEBUGZONE(0)
#define ZONE_WARN       DEBUGZONE(1)
#define ZONE_FUNCTION   DEBUGZONE(2)
#define ZONE_INIT       1 //
#define ZONE_INTR       DEBUGZONE(4)
#define ZONE_RCV        DEBUGZONE(5)
#define ZONE_XMIT       DEBUGZONE(6)

//NDIS Version Declaration
#define DRIVER_NDIS_MAJOR_VERSION 5
#define DRIVER_NDIS_MINOR_VERSION 0

#define DRIVER_NDIS_VERSION        ((DRIVER_NDIS_MAJOR_VERSION << 8) + DRIVER_NDIS_MINOR_VERSION)


//---------------MINIPORT PACKET RELATED--------------------------
//The MINIPORT Packet structure.  One per active send request.
typedef struct  _MINIPORT_PACKET
{
    struct _MINIPORT_PACKET *Next;       //  Next packet on queue.
    UCHAR                   PacketNumber;//  Adapter Packet number.
	USHORT					PacketRange;
} MINIPORT_PACKET;
#define MINIPORT_PACKET_SIZE     sizeof(MINIPORT_PACKET)

//The MINIPORT packet queue structur and macros
typedef struct _MINIPORT_PACKET_QUE
{
    MINIPORT_PACKET  *First;             //  First packet on queue or 0
    MINIPORT_PACKET  *Last;              //  Last packet on queue or &First
} MINIPORT_PACKET_QUE;
#define MAC_PACKET_QUE_SIZE sizeof(MAC_PACKET_QUE)

//The MAC receive context structure.
typedef struct  _MAC_RECEIVE_CONTEXT
{
    UINT            Range;          //  Packet size.
    UCHAR           *PacketData;    //  User data.
} MAC_RECEIVE_CONTEXT;
#define MAC_RECEIVE_CONTEXT_SIZE    sizeof(MAC_RECEIVE_CONTEXT)

//Hardware packet representation.
typedef  struct _SMC_PACK_HEADER
{
    USHORT     Status;
    USHORT     Range;
} SMC_PACK_HEADER;
#define SMC_PACK_HEADER_SIZE    sizeof(SMC_PACK_HEADER)

//Clear packet queue macro.
#define ClearPacketQue(Que) {(Que).First = (MINIPORT_PACKET *) 0;                \
	(Que).Last  = (MINIPORT_PACKET *) &(Que).First;}    \
	
//Test for empty queue macro.
#define IsPacketQueEmpty(Que)  (((Que).First) == (MINIPORT_PACKET *) 0)

//Add a packet to queue macro.
#define QuePacket(Que, _Packet)  {MINIPORT_PACKET *__Last = (Que).Last;   \
	_Packet->Next = (MINIPORT_PACKET *) 0;   \
__Last->Next = (Que).Last = _Packet;}

//Remove a packet from queue macro.
#define DequePacket(Que, Packet) {Packet = (Que).First;                                \
	if(((Que).First = Packet->Next) == (MINIPORT_PACKET *) 0) \
(Que).Last = (MINIPORT_PACKET *) &(Que).First;}        

//Sneak a look at the packet at the head of the queue macro.
#define PeekQue(Que, _Packet) {_Packet = (Que).First;}

//----------------------------------------------------------------

//Multicast Table Entry Structure
#define MAX_MULTICAST_ADDRESS   128

typedef struct 
{
	UINT  MulticastTableEntryCount;
	UCHAR MulticastTableEntry[MAX_MULTICAST_ADDRESS * ETH_LENGTH_OF_ADDRESS];
} MULTICAST_TABLE;


#define TOTAL_BUFFER_SIZE		0x2000
#define MAX_LOOKAHEAD_SIZE      1500
#define LOOK_AHEAD_BUFFER_SIZE  2048
#define MINIPORT_ADAPTER_SIZE   sizeof(MINIPORT_ADAPTER)
#define MAX_FRAME_DATA_SIZE     1500
#define MAX_FRAME_SIZE          ((USHORT)1514)
#define MIN_FRAME_SIZE          14
#define MIN_LEGAL_FRAME_SIZE    64
#define ETHERNET_HEADER_SIZE    14
#define MAC_ADDRESS_SIZE		6
#define MAX_MULTICAST_ADDRESS   128
#define PTR_WAIT                5       //  Loop count waiting after pointer load

#define AUTO_NEGOTIATION         0xFF
#define DEFAULT_VALUE            0xFE
#define FULL_DUPLEX              0x01
#define HALF_DUPLEX              0x00
#define SPEED10                  100000
#define SPEED100                 1000000

#define DEFAULT_IO_BASE         0x300   //  Platform Specific
#define DEFAULT_IRQ             10      //  Platform Specific
#define DEFAULT_MEDIA           0       //  Default media type

#define	CHIPID_LAN91C111		9
#define CHIPREV_LAN91C111_REVA  0
#define CHIPREV_LAN91C111_REVB  1


//--------------------- DRIVER STRUCTURE --------------------------------
typedef  struct _MINIPORT_ADAPTER
{
	NDIS_HANDLE             AdapterHandle;
	UINT					IOBase;				//  Platform Specific - type might have to be changed to accomodate platform specific values
	BOOLEAN                 IsPortRegistered;   //  I/O Port registere with NdisMRegisterIORage (...)
	NDIS_MINIPORT_INTERRUPT InterruptInfo;      //  From NdisMRegisterInterrupt(..)
	USHORT                  InterruptLevel;     //  IRQ in use
	BOOLEAN                 IsInterruptSet;     //  Attached to interrupt using NdisMRegisterInterrupt(...)
	USHORT					InterruptVector;
    USHORT					InterruptType;
	BOOLEAN                 Auto_Negotiation;
	USHORT                  BusType;
    USHORT                  BusNumber;
	USHORT					ConfigReg;          //  Config register to be output
	USHORT					ChipID;				//  Chip ID 
	USHORT					ChipRev;			//  Chip Revision

	UCHAR                   *LookAheadBuffer;   //  Pointer to lookahead buffer
	USHORT                  State;              //  Current state of the Adapter..
	NDIS_OID                LookAhead;          //  Max lookahead size
	BOOLEAN                 Sqet;               //  Enable/disable SQET monitoring
    UINT					Speed;				//  Speed ?? 10/100 
	UCHAR                   Duplex;				//  Duplex ?? FDX/HDX
	UCHAR			        MACAddress[6];		//  Current Station address
	UCHAR                   HashTable[8];       //  Multicast hash bits
	USHORT                  RCR;                //  Updated Receive Control Register.
	USHORT					TCR;				//  Updated Transmit Control Register.
	USHORT					CtrlRegister;
	BOOLEAN                 IsAllocateActive;   //  Is AllocateTxBuffer running?
	BOOLEAN                 IsDpcRunning;       //  Is DPC active?
	BOOLEAN                 AllocateFlag;       //  Allocation in progress
	BOOLEAN                 IsWriteActive;      //  Write in progress
	UINT                    XmitPending;        //  Packets in adapter memory
	UINT                    ChkHangCnt;
	USHORT					LinkStatus;			//  Link Status
	BOOLEAN					NeedIndComplete;	//	Recieve Complete indication
	BOOLEAN					RCVBroadcast;		//	If set recvs broadcasts.
	BOOLEAN					RCVAllMulticast;	//  Rcv All multicasts.
	BOOLEAN					PromiscuousMode;
	BOOLEAN					TxUnderRunFixed;
	MULTICAST_TABLE			MulticastTable;		//	Multicast Table

	MINIPORT_PACKET_QUE     AllocPending;       //  Outbound frames waiting for memory
    MINIPORT_PACKET_QUE     WritePending;       //  Waiting access to write routine
    MINIPORT_PACKET_QUE     AckPending;         //  Waiting completion intr
	NDIS_OID                TransmitQueueDepth; //  Packets on transmit queue
	UCHAR                   MaxXmits;           //  Cap on outstanding transmits

	//Required Statistics.
	UINT					Stat_TxOK;
	UINT					Stat_RxOK;
	UINT					Stat_TxError;
	UINT					Stat_RxError;
	UINT					Stat_RxOvrn;
	UINT					Stat_AlignError;
	UINT					Stat_SingleColl;
	UINT					Stat_MultiColl;

}MINIPORT_ADAPTER, *PMINIPORT_ADAPTER, *PSMSC_ADAPTER;


//-----------------  LAN91C111 Chip Specific Registry Declarations ---------

#define LAN91C111_CHIPID		 9
#define BANK_SELECT             14      //  Offset in IO space to Bank select
#define BANK_ID_MASK            0xff00  //  Mask constant part of bank register
#define BANK_UPPER              0x3300  //  Constant value for upper byte of bank register
#define BANK_MASK               (BANK_UPPER | 3)

//Bank 0 Registers
#define BANK0_TCR               0       //  Transmit control register
#define BANK0_STS               2       //  EPH status register 
#define BANK0_RCR               4       //  Receive control register
#define BANK0_CTR               6       //  Statistics counter register
#define BANK0_MIR               8       //  Memory information register
#define BANK0_RPCR              10      //  Memory configuration register
#define BANK0_RES               12      //  Reserved

//Bank 1 Registers
#define BANK1_CONFIG            0       //  Adapter configuration register
#define BANK1_BASE              2       //  IO Base address
#define BANK1_IA0               4       //  Current address bytes 0-1
#define BANK1_IA2               6       //  Current address bytes 2-3
#define BANK1_IA4               8       //  Current address bytes 4-5
#define BANK1_GEN               10      //  General purpose
#define BANK1_CTL               12      //  Control

//Bank 2 Registers
#define BANK2_MMU_CMD           0       //  MMU command register
#define BANK2_PNR               2       //  Packet Number Register (8 bit)
#define BANK2_ARR               3       //  Allocation Result Register (8 bit)
#define BANK2_FIFOS             4
#define BANK2_TX_FIFO           4       //  Transmit Fifo Port Register (8 bit)
#define BANK2_RX_FIFO           5       //  Receive Fifo Port Register (8 bit)
#define BANK2_PTR               6       //  Pointer Register
#define BANK2_DATA1             8       //  Data Register
#define BANK2_DATA2             10      //  Data Register
#define BANK2_INT_STS           12      //  Interrupt Status Register (8 bit, Read Only)
#define BANK2_INT_ACK           12      //  Interrupt Ack Register (8 bit, Write Only)
#define BANK2_INT_MSK           13      //  Interrupt Mask Register (8 bit, Read/Write)

//Bank 3 Registers
#define BANK3_MT01              0       //  Multicast Hash Table 0-1
#define BANK3_MT23              2       //  Multicast Hash Table 2-3