smc91111.h

嵌入式网卡lan91c的linux源码

#define MII_MDOE	0x0008 // MII Output Enable
#define MII_MCLK	0x0004 // MII Clock, pin MDCLK
#define MII_MDI		0x0002 // MII Input, pin MDI
#define MII_MDO		0x0001 // MII Output, pin MDO


// Revision Register
/* BANK 3 */
#define	REV_REG		0x000A /* ( hi: chip id   low: rev # ) */


// Early RCV Register
/* BANK 3 */
/* this is NOT on SMC9192 */
#define	ERCV_REG	0x000C
#define ERCV_RCV_DISCRD	0x0080 // When 1 discards a packet being received
#define ERCV_THRESHOLD	0x001F // ERCV Threshold Mask

// External Register
/* BANK 7 */
#define	EXT_REG		0x0000


#define CHIP_9192	3
#define CHIP_9194	4
#define CHIP_9195	5
#define CHIP_9196	6
#define CHIP_91100	7
#define CHIP_91100FD	8
#define CHIP_91111FD	9

static const char * chip_ids[ 15 ] =  { 
	NULL, NULL, NULL, 
	/* 3 */ "SMC91C90/91C92",
	/* 4 */ "SMC91C94",
	/* 5 */ "SMC91C95",
	/* 6 */ "SMC91C96",
	/* 7 */ "SMC91C100", 
	/* 8 */ "SMC91C100FD", 
	/* 9 */ "SMC91C11xFD", 
	NULL, NULL, 
	NULL, NULL, NULL};  

/* 
 . Transmit status bits 
*/
#define TS_SUCCESS 0x0001
#define TS_LOSTCAR 0x0400
#define TS_LATCOL  0x0200
#define TS_16COL   0x0010

/*
 . Receive status bits
*/
#define RS_ALGNERR	0x8000
#define RS_BRODCAST	0x4000
#define RS_BADCRC	0x2000
#define RS_ODDFRAME	0x1000	// bug: the LAN91C111 never sets this on receive
#define RS_TOOLONG	0x0800
#define RS_TOOSHORT	0x0400
#define RS_MULTICAST	0x0001
#define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 


// PHY Types
enum {
	PHY_LAN83C183 = 1,	// LAN91C111 Internal PHY
	PHY_LAN83C180
};


// PHY Register Addresses (LAN91C111 Internal PHY)

// PHY Control Register
#define PHY_CNTL_REG		0x00
#define PHY_CNTL_RST		0x8000	// 1=PHY Reset
#define PHY_CNTL_LPBK		0x4000	// 1=PHY Loopback
#define PHY_CNTL_SPEED		0x2000	// 1=100Mbps, 0=10Mpbs
#define PHY_CNTL_ANEG_EN	0x1000 // 1=Enable Auto negotiation
#define PHY_CNTL_PDN		0x0800	// 1=PHY Power Down mode
#define PHY_CNTL_MII_DIS	0x0400	// 1=MII 4 bit interface disabled
#define PHY_CNTL_ANEG_RST	0x0200 // 1=Reset Auto negotiate
#define PHY_CNTL_DPLX		0x0100	// 1=Full Duplex, 0=Half Duplex
#define PHY_CNTL_COLTST		0x0080	// 1= MII Colision Test

// PHY Status Register
#define PHY_STAT_REG		0x01
#define PHY_STAT_CAP_T4		0x8000	// 1=100Base-T4 capable
#define PHY_STAT_CAP_TXF	0x4000	// 1=100Base-X full duplex capable
#define PHY_STAT_CAP_TXH	0x2000	// 1=100Base-X half duplex capable
#define PHY_STAT_CAP_TF		0x1000	// 1=10Mbps full duplex capable
#define PHY_STAT_CAP_TH		0x0800	// 1=10Mbps half duplex capable
#define PHY_STAT_CAP_SUPR	0x0040	// 1=recv mgmt frames with not preamble
#define PHY_STAT_ANEG_ACK	0x0020	// 1=ANEG has completed
#define PHY_STAT_REM_FLT	0x0010	// 1=Remote Fault detected
#define PHY_STAT_CAP_ANEG	0x0008	// 1=Auto negotiate capable
#define PHY_STAT_LINK		0x0004	// 1=valid link
#define PHY_STAT_JAB		0x0002	// 1=10Mbps jabber condition
#define PHY_STAT_EXREG		0x0001	// 1=extended registers implemented

// PHY Identifier Registers
#define PHY_ID1_REG		0x02	// PHY Identifier 1
#define PHY_ID2_REG		0x03	// PHY Identifier 2

// PHY Auto-Negotiation Advertisement Register
#define PHY_AD_REG		0x04
#define PHY_AD_NP		0x8000	// 1=PHY requests exchange of Next Page
#define PHY_AD_ACK		0x4000	// 1=got link code word from remote
#define PHY_AD_RF		0x2000	// 1=advertise remote fault
#define PHY_AD_T4		0x0200	// 1=PHY is capable of 100Base-T4
#define PHY_AD_TX_FDX		0x0100	// 1=PHY is capable of 100Base-TX FDPLX
#define PHY_AD_TX_HDX		0x0080	// 1=PHY is capable of 100Base-TX HDPLX
#define PHY_AD_10_FDX		0x0040	// 1=PHY is capable of 10Base-T FDPLX
#define PHY_AD_10_HDX		0x0020	// 1=PHY is capable of 10Base-T HDPLX
#define PHY_AD_CSMA		0x0001	// 1=PHY is capable of 802.3 CMSA

// PHY Auto-negotiation Remote End Capability Register
#define PHY_RMT_REG		0x05
// Uses same bit definitions as PHY_AD_REG

// PHY Configuration Register 1
#define PHY_CFG1_REG		0x10
#define PHY_CFG1_LNKDIS		0x8000	// 1=Rx Link Detect Function disabled
#define PHY_CFG1_XMTDIS		0x4000	// 1=TP Transmitter Disabled
#define PHY_CFG1_XMTPDN		0x2000	// 1=TP Transmitter Powered Down
#define PHY_CFG1_BYPSCR		0x0400	// 1=Bypass scrambler/descrambler
#define PHY_CFG1_UNSCDS		0x0200	// 1=Unscramble Idle Reception Disable
#define PHY_CFG1_EQLZR		0x0100	// 1=Rx Equalizer Disabled
#define PHY_CFG1_CABLE		0x0080	// 1=STP(150ohm), 0=UTP(100ohm)
#define PHY_CFG1_RLVL0		0x0040	// 1=Rx Squelch level reduced by 4.5db
#define PHY_CFG1_TLVL_SHIFT	2	// Transmit Output Level Adjust
#define PHY_CFG1_TLVL_MASK	0x003C
#define PHY_CFG1_TRF_MASK	0x0003	// Transmitter Rise/Fall time


// PHY Configuration Register 2
#define PHY_CFG2_REG		0x11
#define PHY_CFG2_APOLDIS	0x0020	// 1=Auto Polarity Correction disabled
#define PHY_CFG2_JABDIS		0x0010	// 1=Jabber disabled
#define PHY_CFG2_MREG		0x0008	// 1=Multiple register access (MII mgt)
#define PHY_CFG2_INTMDIO	0x0004	// 1=Interrupt signaled with MDIO pulseo

// PHY Status Output (and Interrupt status) Register
#define PHY_INT_REG		0x12	// Status Output (Interrupt Status)
#define PHY_INT_INT		0x8000	// 1=bits have changed since last read
#define	PHY_INT_LNKFAIL		0x4000	// 1=Link Not detected
#define PHY_INT_LOSSSYNC	0x2000	// 1=Descrambler has lost sync
#define PHY_INT_CWRD		0x1000	// 1=Invalid 4B5B code detected on rx
#define PHY_INT_SSD		0x0800	// 1=No Start Of Stream detected on rx
#define PHY_INT_ESD		0x0400	// 1=No End Of Stream detected on rx
#define PHY_INT_RPOL		0x0200	// 1=Reverse Polarity detected
#define PHY_INT_JAB		0x0100	// 1=Jabber detected
#define PHY_INT_SPDDET		0x0080	// 1=100Base-TX mode, 0=10Base-T mode
#define PHY_INT_DPLXDET		0x0040	// 1=Device in Full Duplex

// PHY Interrupt/Status Mask Register
#define PHY_MASK_REG		0x13	// Interrupt Mask
// Uses the same bit definitions as PHY_INT_REG



/*-------------------------------------------------------------------------
 .  I define some macros to make it easier to do somewhat common
 . or slightly complicated, repeated tasks. 
 --------------------------------------------------------------------------*/

/* select a register bank, 0 to 3  */

#define SMC_SELECT_BANK(x)  { outw( x, ioaddr + BANK_SELECT ); } 

/* this enables an interrupt in the interrupt mask register */
#define SMC_ENABLE_INT(x) {\
		unsigned char mask;\
		SMC_SELECT_BANK(2);\
		mask = inb( ioaddr + IM_REG );\
		mask |= (x);\
		outb( mask, ioaddr + IM_REG ); \
}

/* this disables an interrupt from the interrupt mask register */

#define SMC_DISABLE_INT(x) {\
		unsigned char mask;\
		SMC_SELECT_BANK(2);\
		mask = inb( ioaddr + IM_REG );\
		mask &= ~(x);\
		outb( mask, ioaddr + IM_REG ); \
}

/*----------------------------------------------------------------------
 . Define the interrupts that I want to receive from the card
 . 
 . I want: 
 .  IM_EPH_INT, for nasty errors
 .  IM_RCV_INT, for happy received packets
 .  IM_RX_OVRN_INT, because I have to kick the receiver
 .  IM_MDINT, for PHY Register 18 Status Changes
 --------------------------------------------------------------------------*/
#define SMC_INTERRUPT_MASK   (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
	IM_MDINT) 


#ifdef CONFIG_SYSCTL


/*
 * Declarations for the sysctl interface, which allows users the ability to
 * control the finer aspects of the LAN91C111 chip.  Since the smc
 * module currently registers its sysctl table dynamically, the sysctl path
 * for module FOO is /proc/sys/dev/ethX/FOO
 */
#define CTL_SMC         (CTL_BUS+1389)      // arbitrary and hopefully unused

enum {
	CTL_SMC_INFO = 1,	// Sysctl files information
	CTL_SMC_SWVER,		// Driver Software Version Info
	CTL_SMC_SWFDUP,		// Switched Full Duplex Mode
	CTL_SMC_EPHLOOP,	// EPH Block Internal Loopback
	CTL_SMC_MIIOP,		// MII Operation
	CTL_SMC_AUTONEG,	// Auto-negotiate Mode
	CTL_SMC_RFDUPLX,	// Request Full Duplex Mode
	CTL_SMC_RSPEED,		// Request Speed Selection
	CTL_SMC_AFDUPLX,	// Actual Full Duplex Mode
	CTL_SMC_ASPEED,		// Actual Speed Selection
	CTL_SMC_LNKFAIL,	// Link Failed
	CTL_SMC_FORCOL,		// Force a Collision
	CTL_SMC_FILTCAR,	// Filter Carrier
	CTL_SMC_FREEMEM,	// Free Buffer Memory
	CTL_SMC_TOTMEM,		// Total Buffer Memory
	CTL_SMC_LEDA,		// Output of LED-A
	CTL_SMC_LEDB,		// Output of LED-B
	CTL_SMC_CHIPREV,	// LAN91C111 Chip Revision ID
#ifdef SMC_DEBUG
	// Register access for debugging
	CTL_SMC_REG_BSR,	// Bank Select
	CTL_SMC_REG_TCR,	// Transmit Control
	CTL_SMC_REG_ESR,	// EPH Status
	CTL_SMC_REG_RCR,	// Receive Control
	CTL_SMC_REG_CTRR,	// Counter
	CTL_SMC_REG_MIR,	// Memory Information
	CTL_SMC_REG_RPCR,	// Receive/Phy Control
	CTL_SMC_REG_CFGR,	// Configuration
	CTL_SMC_REG_BAR,	// Base Address
	CTL_SMC_REG_IAR0,	// Individual Address 0
	CTL_SMC_REG_IAR1,	// Individual Address 1 
	CTL_SMC_REG_IAR2,	// Individual Address 2
	CTL_SMC_REG_GPR,	// General Purpose
	CTL_SMC_REG_CTLR,	// Control
	CTL_SMC_REG_MCR,	// MMU Command
	CTL_SMC_REG_PNR,	// Packet Number
	CTL_SMC_REG_FPR,	// FIFO Ports
	CTL_SMC_REG_PTR,	// Pointer
	CTL_SMC_REG_DR,		// Data 
	CTL_SMC_REG_ISR,	// Interrupt Status
	CTL_SMC_REG_MTR1,	// Multicast Table Entry 1
	CTL_SMC_REG_MTR2,	// Multicast Table Entry 2
	CTL_SMC_REG_MTR3,	// Multicast Table Entry 3
	CTL_SMC_REG_MTR4,	// Multicast Table Entry 4
	CTL_SMC_REG_MIIR,	// Management Interface
	CTL_SMC_REG_REVR,	// Revision
	CTL_SMC_REG_ERCVR,	// Early RCV
	CTL_SMC_REG_EXTR,	// External
	CTL_SMC_PHY_CTRL,	// PHY Control
	CTL_SMC_PHY_STAT,	// PHY Status
	CTL_SMC_PHY_ID1,	// PHY ID1
	CTL_SMC_PHY_ID2,	// PHY ID2
	CTL_SMC_PHY_ADC,	// PHY Advertise Capability
	CTL_SMC_PHY_REMC,	// PHY Advertise Capability
	CTL_SMC_PHY_CFG1,	// PHY Configuration 1
	CTL_SMC_PHY_CFG2,	// PHY Configuration 2
	CTL_SMC_PHY_INT,	// PHY Interrupt/Status Output
	CTL_SMC_PHY_MASK,	// PHY Interrupt/Status Mask
#endif
	// ---------------------------------------------------
	CTL_SMC_LAST_ENTRY	// Add new entries above the line
};

#endif // CONFIG_SYSCTL
 
#endif  /* _SMC_91111_H_ */