t89c51ix2_sys.h

ix2-lib-spi-1_2_0.zip源码

/*H**************************************************************************
* NAME: t89c51ix2_sys.h          
*----------------------------------------------------------------------------
* Copyright (c) 2001 ATMEL.
*----------------------------------------------------------------------------
*----------------------------------------------------------------------------
* PURPOSE: 
* This file provides common defines and macros for use wit T89c51ix2 products                         
*****************************************************************************/




/* IRQ definition */

#define IRQ_INT0  0
#define IRQ_TIMER0  1
#define IRQ_INT1  2
#define IRQ_TIMER1  3
#define IRQ_UART  4
#define IRQ_TIMER2  5
#define IRQ_PCA   6
#define IRQ_KBD   7
#define IRQ_TWI   8
#define IRQ_SPI   9

/* Interrupt Enable */
#define ENABLE_INT0_IT    EX0=1;        
#define DISABLE_INT0_IT   EX0=0;      
#define ENABLE_TIMER0_IT  ET0=1;        
#define DISABLE_TIMER0_IT ET0=0;      
#define ENABLE_INT1_IT    EX1=1;        
#define DISABLE_INT1_IT   EX1=0;      
#define ENABLE_TIMER1_IT  ET1=1;      
#define DISABLE_TIMER1_IT ET1=0;      
#define ENABLE_UART_IT    ES=1;       
#define DISABLE_UART_IT   ES=0;       
#define ENABLE_TIMER2_IT  ET2=1;      
#define DISABLE_TIMER2_IT ET2=0;      
#define ENABLE_PCA_IT     EC=1;       
#define DISABLE_PCA_IT    EC=0;       
#define ENABLE_IT         EA=1;       
#define DISABLE_IT        EA=0;       
#define ENABLE_KBD_IT     IEN1 |= 0x01;
#define DISABLE_KBD_IT    IEN1 &= 0xFE;
#define ENABLE_TWI_IT     IEN1 |= 0x02;
#define DISABLE_TWI_IT    IEN1 &= 0xFD;
#define ENABLE_SPI_IT     IEN1 |= 0x04;
#define DISABLE_SPI_IT    IEN1 &= 0xFB;


/* X2 Config */
#define SET_X2_CORE         CKCON0 |= 0x01;
#define CLEAR_X2_CORE       CKCON0 &= 0XFE;
#define CLEAR_X2_TIMER0     CKCON0 |= 0x02;
#define SET_X2_TIMER0       CKCON0 &= 0XFD;
#define CLEAR_X2_TIMER1     CKCON0 |= 0x04;
#define SET_X2_TIMER1       CKCON0 &= 0XFB;
#define CLEAR_X2_TIMER2     CKCON0 |= 0x08;
#define SET_X2_TIMER2       CKCON0 &= 0XF7;
#define CLEAR_X2_UART       CKCON0 |= 0x10;
#define SET_X2_UART         CKCON0 &= 0XEF;
#define CLEAR_X2_PCA        CKCON0 |= 0x20;
#define SET_X2_PCA          CKCON0 &= 0XDF;
#define CLEAR_X2_WD         CKCON0 |= 0x40;
#define SET_X2_WD           CKCON0 &= 0XBF;
#define CLEAR_X2_TWI        CKCON0 |= 0x80;
#define SET_X2_TWI          CKCON0 &= 0X7F;
#define CLEAR_SPI_SPI        CKCON1 |= 0x01;  
#define SET_SPI_SPI          CKCON1 &= 0XFE;

#define SET_XRAM_0        { AUXR |= 0x02; }
#define SET_XRAM_256      { AUXR &= 0xFE; }
#define SET_XRAM_512      { AUXR &= 0xF4; AUXR |= 0x04; }
#define SET_XRAM_768      { AUXR &= 0xF8; AUXR |= 0x08; }
#define SET_XRAM_1024     { AUXR &= 0xFC; AUXR |= 0x0C; }