m6117.8

PC x386 bios source code

	;
	; System specific code
	;
	; ALI M6117 chipset
	;
	; (C)1997 Pascal Dornier / PC Engines; All rights reserved.
	; This file is licensed pursuant to the COMMON PUBLIC LICENSE 0.5.
	;
	
	; Note: The M6117B version has a bug in chipset register access:
	; if a ISA refresh cycle comes between the index and data access,
	; the index register is reset. To avoid this, we have to stop
	; refresh during register updates.
	
	; M6117C defaults to EDO memory.
	
	; We don't use memory remap, too many strings attached. If you really
	; need the memory, I suggest enabling shadow for the upper memory
	; and using it as a upper memory block.
	
	; Fast ISA I/O can be enabled for port 1Fx (IDE interface), this
	; improves hard disk transfer rate by about 25%, but seems to cause
	; some side effects.
	
	; Page number refer to ver 1.2 data sheet. c??? -> 11/11/97 M6117C.

	;
	; Equates
	;
idx	equ	22h	;configuration index register
dat	equ	23h	;configuration data register

TOP_MEM	equ	0100	;memory size limit = 16 MB
	
M6117:			;disables use of WBINVD instruction
			;in BIOS core.
			
	;
	; clear chipset registers before initializing DMA, IRQ
	;
cs_clr:	ret
	;
	; initialize chipset
	;
	; set all registers, detect memory size
	; keep L2 cache disabled at this point
	; set CPU specific registers if required
	;
cs_init:
#if def	M6117B
	mov	al,50h	;stop refresh
	out	timer+3,al
	out	iowait,ax
	out	iowait,ax
#endif	
	mov	al,13h	;b43 c42 unlock register access
	out	idx,al
	mov	al,0c5h
	out	dat,al
	mov	bl,0	;clear shadow flag
	mov	si,offset cs_tab
	mov	al,15h	;b44 c42 E,F shadow
	out	idx,al
	in	al,dat	;are we in shadow mode ?
	test	al,40h
	jz	cs_ini1	;:no
	mov	si,offset cs_tab2	;skip shadow, memory config settings
	inc	bx	;set shadow flag
cs_ini1:	cs:	lodsw	;get index / data from table
	cmp	al,0ffh
	jz	cs_ini2	;:end
	out	idx,al
	mov	al,ah
	out	dat,al
	jmp	cs_ini1
cs_ini2:
#if def	M6117B
	mov	al,54h	;restart refresh
	out	timer+3,al
	mov	al,12h
	out	timer+1,al
#endif
	shr	bx,1	;shadow flag -> carry
	ret		;no carry = full initialization
	;
	; CPU specific settings
	;
cs_cpu:	ret
	;
	; Detect memory
	;
cs_det:	mov	bp,sp	;save SP
	ret_sp	getunreal	;enter unreal mode

	; cs_init sets memory type 30 = 4 x 4MB

	; detect type of bank 2 and 3, can be 256KB, 1MB or 4 MB.

	mov	ax,55aah	;test pattern 1
	mov	bx,33cch	;test pattern 2
	mov	cx,2	;2 banks
	mov	di,3000h	;start with bank 3

cs_det2:	shl	dx,4	;save previous memory type
	mov	[di],ax	;write first pattern
	mov	[di+4],bx	;invert bus
	cmp	[di],ax	;did it stick ?
	jnz	cs_det3	;:nothing in this bank, DL=0
	inc	dx	;DL=01: 256KB
	mov	[di+0400h],bx	;test A10
	cmp	[di],ax	;destroyed ?
	jnz	cs_det3	;:was 256 KB or 512 KB
	inc	dx	;DL=03: 1MB
	inc	dx
	mov	[di+0800h],bx	;test A11
	cmp	[di],ax	;destroyed ?
	jnz	cs_det3	;:was 1MB or 2MB
	inc	dx	;DL=05: 4MB
	inc	dx
cs_det3:	sub	di,1000h
	loop	cs_det2	;:next bank

	; to detect banks 0 and 1, use mode 31 (2 x 16MB)
	
	mov	ah,10h	;read register
	ret_sp	cs_get
	or	al,0f8h	;set mode 31
	ret_sp	cs_set

	; detect banks 0 and 1
	
	mov	ax,55aah	;test pattern 1
	mov	bx,33cch	;test pattern 2
	mov	edi,2000h	;start with bank 1
cs_det6:	shl	dx,4	;save previous memory type
	mov	[di],ax	;write first pattern
	mov	[di+4],bx	;flip bus
	cmp	[di],ax	;did it stick ?
	jnz	cs_det9	;:nothing in this bank, DL=0
	inc	dx	;DL=01: 256KB
	mov	[di+0400h],bx	;test A10
	cmp	[di],ax	;destroyed ?
	jz	cs_det7	;:no

	; 256KB or 512KB ? test A20
	
	mov	[di],ax	;restore pattern
	mov 	[edi+100000h],bx
	jmp	short cs_det9

cs_det7:	inc	dx	;DL=03: 1MB
	inc	dx
	mov	[di+0800h],bx	;test A11
	cmp	[di],ax	;destroyed ?
	jz	cs_det8	;:no

	; 1MB or 2MB ? test A24

	mov	[di],ax	;restore pattern
	mov 	[edi+1000000h],bx
	jmp	short cs_det9	
	
cs_det8:	inc	dx	;DL=05: 4MB
	inc	dx
	mov	[di+1000h],bx	;test A12
cs_det9:	cmp	[di],ax	;destroyed ?
	jnz	cs_det10	;:was 4MB
	inc	dx	;DL=06: 16MB

cs_det10:	sub	di,2000h	;bank 0
	jz	cs_det6	;:next bank
	
	xor	ax,ax	;restore DS,ES
	mov	ds,ax
	mov	es,ax
	
	; find the memory configuration in table

	mov	si,offset cs_mtab	;memory configuration table
	mov	cx,32	;32 configurations
cs_det11:	cmp	dx,[cs:si]	;does the configuration match ?
	jz	cs_det12	;:yes
	lea	si,[si+4]	;next entry
	loop	cs_det11
cs_det12:	mov	cx,[cs:si+2]	;get mode (CL) and size (CH)
	
	mov	ah,10h	;get memory config
	ret_sp	cs_get
	and	al,07
	or	al,cl	;set new configuration
	ret_sp	cs_set
	mov	sp,bp	;restore SP
	ret
	;
	; Copy BIOS to shadow RAM (skip if already enabled)
	;
	; Note: For fastest startup, this happens before DRAM test and
	; BIOS checksum test. If DRAM or BIOS is bad, we might crash.
	;
cs_shad:	mov	ah,15h	;check shadow status
	ret_sp	cs_get
	test	al,50h	;enabled ?
	jnz	cs_shad9	;yes: don't do again (implicit clear C)
	mov	bx,ax	;save register setting
	
	mov	ax,cs	;copy BIOS to shadow RAM
	mov	ds,ax
	mov	es,ax
	xor	si,si
	xor	di,di
	mov	cx,4000h
	rep 	movsd	;rep movsd
	
	mov	ax,bx	;restore register setting
	or	al,50h	;enable shadow read
	ret_sp	cs_set	;set register
	stc		;set C = new shadow
cs_shad9:	jmp	rstshad2
	;
	; Copy video BIOS to shadow RAM
	;
cs_vshad:	push	ds
	push	es
	mov	ah,14h	;b44 c42 video shadow enabled ?
	call	cs_get
	test	al,1
	jnz	cs_vshad1	;:yes
	mov	bx,ax	;save setting
	or	al,2	;set write
	call	cs_set
	
	mov	ax,0c000h	;copy video BIOS from ROM to shadow
	mov	ds,ax
	mov	es,ax
	xor	si,si
	xor	di,di
	mov	cx,8000h/4
	rep 	movsd
	
	mov	ax,bx	;restore register setting
	or	al,1	;enable read
	call	cs_set
cs_vshad1: pop	es	;restore segment
	pop	ds
	ret
	;
	; set speed-sensitive chipset registers
	;
cs_spd:	ret
	;
	; Set read/write shadow
	;
	; The BIOS is written to for HDD parameters.
	;
cs_shadrw: mov	ah,15h	;b44 c42 E,F shadow status
	call	cs_get
	or	al,0a0h
	jmp	short cs_set
	;
	; set read only shadow
	;
cs_shadro: mov	ah,15h	;b44 c42 E,F shadow status
	call	cs_get
	and	al,5fh	;disable write
	jmp	short cs_set
	;
	; Wait BX milliseconds - depends on refresh rate !!!
	;
	; This is used for floppy delays and INT15 function 86.
	;
cs_waitbx: inc	bx
	jmp	short cs_wbx8
	
cs_wbx1:	mov	cx,62	;62 refresh cycles per millisecond
cs_wbx2:	in	al,port61
	and	al,10h
	mov	ah,al
cs_wbx3:	in	al,port61	;wait for refresh bit to change state
	and	al,10h
	cmp	al,ah
	jz	cs_wbx3
          loop	cs_wbx2	;:another iteration
cs_wbx8:	dec	bx	;another millisecond ?
	jnz	cs_wbx1
cs_wbx9:	ret
	;
	; Test and enable numeric coprocessor - not supported
	;
cs_npx:	ret
	;
	; get register [AH]->AL	(BX clobbered)
	;
cs_get:
#if def	M6117B
	mov	al,50h	;stop refresh
	out	timer+3,al
	out	iowait,ax
	out	iowait,ax
#endif
	mov	al,ah
	out	idx,al	;write index
	in	al,dat	;read chipset register
#if def	M6117B
	xchg	bx,ax	;save AX
	mov	al,54h	;restart refresh
	out	timer+3,al
	mov	al,12h
	out	timer+1,al
	xchg	bx,ax	;restore AX
#endif
	ret
	;
	; enable A20 gate
	;
cs_a20on:	mov	ah,31h
	call	cs_get
	or	al,1	;enable A20 gate
	;
	; set register AL->[AH]	(BX clobbered)
	;
cs_set:
#if def	M6117B
	xchg	bx,ax	;save AX
	mov	al,50h	;stop refresh
	out	timer+3,al
	out	iowait,ax
	out	iowait,ax
	xchg	bx,ax	;restore AX
#endif	
	xchg	al,ah
	out	idx,al	;write index
	mov	al,ah
	out	dat,al
#if def	M6117B
	mov	al,54h	;restart refresh
	out	timer+3,al
	mov	al,12h
	out	timer+1,al
#endif
	ret
	;
	; Memory configuration table
	;
	; Bytes 0,1: memory type per bank (one nibble per bank)
	; Byte  2  : register setting
	; Byte  3  : size in MB
	;
	; If the setting doesn't match, last entry ("mode 32") is used
	; to provide for a limp home mode.
	;
	even
cs_mtab:	dw	0011h,0100h	;mode 0:   1MB
	dw	1111h,0210h	;mode 1:   2MB
	dw	0311h,0320h	;mode 2:   3MB
	dw	3311h,0530h	;mode 3:   5MB
	dw	0511h,0940h	;mode 4:   9MB
	dw	0002h,0150h	;mode 5:   1MB
	dw	0022h,0260h	;mode 6:   2MB
	dw	0322h,0470h	;mode 7:   4MB
	dw	3322h,0680h	;mode 8:   6MB
	dw	0522h,0a90h	;mode 9:  10MB
	dw	5522h,12a0h	;mode 10: 18MB
	dw	0032h,03b0h	;mode 11:  3MB
	dw	0332h,05c0h	;mode 12:  5MB
	dw	0052h,09d0h	;mode 13:  9MB
	dw	0003h,02e0h	;mode 14:  2MB
	dw	0033h,04f0h	;mode 15:  4MB
	dw	0333h,0608h	;mode 16:  6MB
	dw	3333h,0818h	;mode 17:  8MB
	dw	0533h,0c28h	;mode 18: 12MB
	dw	5533h,1438h	;mode 19: 20MB
	dw	0053h,0a48h	;mode 20: 10MB
	dw	0553h,1258h	;mode 21: 18MB
	dw	5553h,1a68h	;mode 22: 26MB
	dw	0004h,0478h	;mode 23:  4MB
	dw	0044h,0888h	;mode 24:  8MB
	dw	5544h,1898h	;mode 25: 24MB
	dw	0054h,0ca8h	;mode 26: 12MB
	dw	0005h,08b8h	;mode 27:  8MB
	dw	0055h,10c8h	;mode 28: 16MB
	dw	0555h,18d8h	;mode 29: 24MB
	dw	5555h,20e8h	;mode 30: 32MB
	dw	0066h,40f8h	;mode 31: 64MB
	dw	0033h,04f0h	;mode 15:  4MB fall-back
	;
	; M6117 chipset init table
	;
cs_tab:	db	010,0e8	;b43 c41 ROM size 64KB, RAS only refresh,
			;4MBx4 DRAM type
			;EA: CAS before RAS refresh
	db	014,000	;b44 c42 C,D shadow = disable
	db	015,0a0	;b44 c42 E,F shadow = write enable
	;
	; The following registers can be reinitialized even when we are
	; already running out of shadow memory.
	;
cs_tab2:	db	011,001	;b43 c41 Memory controller 01 = fastest
			;timing, no remap
	db	012,010	;b43 c41 Split address, misc
	db	016,000	;b44 c42 fast ISA mem 1 A23..16
	db	017,0FF	;b44 c42 fast ISA mem 1 A23..16 mask
	db	018,0F0	;b44 c43 fast ISA mem 1 A15..12
	db	019,000	;b45 c43 fast ISA mem 2 A23..16
	db	01A,0FF	;b45 c43 fast ISA mem 2 A23..16 mask
	db	01B,0F0	;b45 c43 fast ISA mem 2 A15..12
	db	01C,hdc/4	;b45 c43 fast ISA I/O A9..2 -> IDE
			;interface
	db	01D,0FF	;b45 c43 fast ISA I/O A9..2 mask
	db	01E,006	;b45 c43 ISA clock PCLK2/10
;	db	01F,000	;
	db	020,080	;b45 c43 DRAM enable, no SMI remap, no
			;flash write
	db	031,015	;b46 c44 fast RC, gate A20
	db	032,000	;b46 c44 fast I/O disable
			;080 to enable
	db	033,04e	;b46 c44 I/O recovery 1us
			;040 to disable I/O recovery
			;04e for 1us I/O recovery
	db	036,080	;b47 c45 16 bit ISA 1 wait, PS/2 mouse
			;IRQ disable, 15us refresh
;	db	037,000	;

#if def	M6117C
	db	037,003	;c45 disable watchdog, mouse
			;enable IDE, EDO mode
	db	03c,000	;primary IDE
#endif	
	; PMU registers - we don't use power management
	
	db	055,008	;47 PMU config - off
	db	056,000	;47 PMU config - off
	db	057,000	;47 Idle detect mode - off
	db	058,000	;47 SMI source select - off
	db	059,000	;47 Timer time-out select - off
	db	05A,000	;47 Peripheral access select - off
	db	05B,000	;48 SMI cause - off
	db	05C,000	;48 IRQ event channel 1 - off
	db	05D,000	;48 IRQ event channel 2 - off
	db	05E,000	;48 DRQ event channel - off
	db	064,000	;48 Mode timer - off
	db	066,000	;48 VGA, IN monitor setting - off
	db	067,000	;49 EXTSW1, EXTSW2 polarity - off
#if def	M6117B		;this is for eval board only
	db	068,0FD	;49 Power on latch: set 80 MHz clock
#endif
	db	069,000	;49 Timer counter status
	db	06A,000	;49 R/O Doze, standby, suspend timer status
	db	06B,000	;49 GP1 address - off
	db	06C,000	;50 GP0 address A23..16
	db	06D,000	;50 GP0 address A23..16 mask
	db	06E,000	;50 GP0 address A25..24
	db	06F,000	;50 GP0 address A25..24 mask
	db	070,000	;50 GP1 I/O address A9..2
	db	071,000	;50 Mode LED function
;	db	072,00F	;50 Port 70 shadow
#if def	M6117
	db	073,0FE	;50 W/O set clock frequency
#endif
	db	0ff	;end of table