📄 dac0832s.mdf
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LISA MODEL DESCRIPTION FORMAT 6.1
=================================
Design: K:\CustSupport\Custom Models\DAC0832\DAC0832S.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author: <NONE>
Created: 13/12/06
Modified: 14/12/06
*PROPERTIES,0
*MODELDEFS,0
*PARTLIST,10
ANALOG_G1,VCCS,-1.0,PRIMITIVE=ANALOGUE
ANALOG_G2,VCCS,-1.0,PRIMITIVE=ANALOGUE
ANALOG_H1,CCVS,1,PRIMITIVE=ANALOGUE
DAC1,DAC_8,DAC_8,MODDLL=DATAC,MODE=UNSIGNED,PRIMITIVE=PASSIVE,SLEWRATE=1E6,TDDA=0
R1,RESISTOR,4.2k,PRIMITIVE=ANALOGUE
RFB,RESISTOR,15k,PRIMITIVE=ANALOGUE
RLADDER,RESISTOR,15k,PRIMITIVE=ANALOGUE
U1,LATCH_8,LATCH_8,EDGE=0,INVERT=OE,PRIMITIVE=DIGITAL
U2,NOR_2,NOR_2,PRIMITIVE=DIGITAL
U3,NOR_2,NOR_2,PRIMITIVE=DIGITAL
*NETLIST,32
#00008,2
U1,OP,Q0
DAC1,IP,D0
#00010,2
U1,OP,Q1
DAC1,IP,D1
#00011,2
U1,OP,Q2
DAC1,IP,D2
#00012,2
U1,OP,Q3
DAC1,IP,D3
#00013,2
U1,OP,Q4
DAC1,IP,D4
#00014,2
U1,OP,Q5
DAC1,IP,D5
#00015,2
U1,OP,Q6
DAC1,IP,D6
#00016,2
U1,OP,Q7
DAC1,IP,D7
#00017,2
U1,IP,CLK
U2,OP,Q
#00024,2
DAC1,IP,LE
U3,OP,Q
DI1,2
DI1,GT
U1,IP,D1
DI2,2
DI2,GT
U1,IP,D2
DI3,2
DI3,GT
U1,IP,D3
DI4,2
DI4,GT
U1,IP,D4
DI5,2
DI5,GT
U1,IP,D5
DI6,2
DI6,GT
U1,IP,D6
DI7,2
DI7,GT
U1,IP,D7
DI0,2
DI0,GT
U1,IP,D0
ILE(BY1/$BY2$),2
ILE(BY1/$BY2$),GT
U1,IP,EN
$CS,2
$CS,GT
U2,IP,D0
$WR1,2
$WR1,GT
U2,IP,D1
$WR2,2
$WR2,GT
U3,IP,D0
$XFER,2
$XFER,GT
U3,IP,D1
RFB,2
RFB,GT
RFB,PS,1
VCC,2
VCC,GT
R1,PS,1
IOUT1,3
IOUT1,GT
ANALOG_G1,PS,+
RFB,PS,2
GND,10
GND,PT
ANALOG_G1,PS,-
ANALOG_G1,PS,N
ANALOG_G2,PS,-
ANALOG_H1,PS,-
DAC1,PS,VREF-
RLADDER,PS,2
R1,PS,2
U1,IP,OE
U1,PS,RESET
#00021,3
ANALOG_G1,PS,P
ANALOG_G2,PS,N
DAC1,PS,VOUT
VREF,2
VREF,GT
ANALOG_H1,PS,P
#00022,3
ANALOG_H1,PS,+
ANALOG_G2,PS,P
DAC1,PS,VREF+
#00030,2
ANALOG_H1,PS,N
RLADDER,PS,1
IOUT2,2
IOUT2,GT
ANALOG_G2,PS,+
*GATES,0
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