crt0.s

来自「IBM PowerPC 405 在DiabData开发环境下的ucosII移植代」· S 代码 · 共 815 行 · 第 1/3 页

    addis   r3,0,0x001E
    ori     r3,r3,0x8480          # ensure 10msec have passed since reset
    mtctr   r3
..spinlp3:
    bdnz    ..spinlp3             # spin loop

    mtlr    r31                   # restore lr
    blr


;-----------------------------------------------------------------------------
; Function:     ext_bus_cntlr_init
; Description:  Initializes the External Bus Controller for the external 
;		peripherals. IMPORTANT: For pass1 this code must run from 
;		cache since you can not reliably change a peripheral banks
;		timing register (pbxap) while running code from that bank.
;		For ex., since we are running from ROM on bank 0, we can NOT 
;		execute the code that modifies bank 0 timings from ROM, so
;		we run it from cache.
;	Bank 0 - Flash/SRAM 
;	Bank 1 - NVRAM/RTC
;	Bank 2 - KYBD/Mouse Controller
;	Bank 3 - IRDA
;	Bank 4 - Pinned out to Expansion connector
;	Bank 5 - Pinned out to Expansion connector
;	Bank 6 - Pinned out to Expansion connector
;	Bank 7 - FPGA regs 
;-----------------------------------------------------------------------------
        .text
        .align 2
        .globl  ext_bus_cntlr_init

ext_bus_cntlr_init:

        addis   r4,r0, I_CACHEABLE_REGIONS@h
        ori     r4,r4, I_CACHEABLE_REGIONS@l

        mficcr  r9                     ; get iccr value
        cmp     cr0,0,r9,r4          ; check if caching already enabled
        beq     ..icache_on             ; if not,
        mticcr  r4                     ; enable caching 
..icache_on:
        addis   r3,0,ext_bus_cntlr_init@h    ; store the address of the 
        ori     r3,r3,ext_bus_cntlr_init@l  ; ext_bus_cntlr_init functn in r3
        addi    r4,0,11                ; set ctr to 10; used to prefetch
        mtctr   r4                     ; 10 cache lines to fit this function
                                        ; in cache (gives us 8x10=80 instrctns)
..ebcloop:
        icbt    r0,r3                 ; prefetch cache line for addr in r3
        addi    r3,r3,32		; move to next cache line
        bdnz    ..ebcloop               ; continue for 10 cache lines

        ;-------------------------------------------------------------------
        ; Delay to ensure all accesses to ROM are complete before changing
	; bank 0 timings. 200usec should be enough.
        ;   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
        ;-------------------------------------------------------------------
	addis	r3,0,0x0
        ori     r3,r3,0xA000          ; ensure 200usec have passed since reset
        mtctr   r3
..spinlp:
        bdnz    ..spinlp                ; spin loop

        ;-----------------------------------------------------------------------
        ; Memory Bank 0 (Flash/SRAM) initialization
        ;-----------------------------------------------------------------------
        addi    r4,0,pb0ap
        mtdcr   ebccfga,r4
        addis   r4,0,0x9B01
        ori     r4,r4,0x5480
        mtdcr   ebccfgd,r4

        addi    r4,0,pb0cr
        mtdcr   ebccfga,r4
        addis   r4,0,0xFFF1            ; BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W),
        ori     r4,r4,0x8000          ; BW=0x0(8 bits)
        mtdcr   ebccfgd,r4

        ;-----------------------------------------------------------------------
        ; Memory Bank 1 (NVRAM/RTC) initialization
        ;-----------------------------------------------------------------------
        addi    r4,0,pb1ap
        mtdcr   ebccfga,r4
        addis   r4,0,0x0281         
        ori     r4,r4,0x5480
        mtdcr   ebccfgd,r4

        addi    r4,0,pb1cr
        mtdcr   ebccfga,r4
        addis   r4,0,0xF001            ; BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),
        ori     r4,r4,0x8000            ; BW=0x0(8 bits)
        mtdcr   ebccfgd,r4

        ;-----------------------------------------------------------------------
        ; Memory Bank 2 (KYBD/Mouse) initialization
        ;-----------------------------------------------------------------------
        addi    r4,0,pb2ap
        mtdcr   ebccfga,r4
        addis   r4,0,0x0481
        ori     r4,r4,0x5A80
        mtdcr   ebccfgd,r4

        addi    r4,0,pb2cr
        mtdcr   ebccfga,r4
        addis   r4,0,0xF011            ; BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),
        ori     r4,r4,0x8000            ; BW=0x0(8 bits)
        mtdcr   ebccfgd,r4

        ;-----------------------------------------------------------------------
        ; Memory Bank 3 (IRDA) initialization
        ;-----------------------------------------------------------------------
        addi    r4,0,pb3ap
        mtdcr   ebccfga,r4
        addis   r4,0,0x0181         
        ori     r4,r4,0x5280
        mtdcr   ebccfgd,r4

        addi    r4,0,pb3cr
        mtdcr   ebccfga,r4
        addis   r4,0,0xF021            ; BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),
        ori     r4,r4,0x8000            ; BW=0x0(8 bits)
        mtdcr   ebccfgd,r4

        ;-----------------------------------------------------------------------
        ; Memory Bank 7 (FPGA regs) initialization
        ;-----------------------------------------------------------------------
        addi    r4,0,pb7ap
        mtdcr   ebccfga,r4
        addis   r4,0,0x0181            ; TWT=3  
        ori     r4,r4,0x5280
        mtdcr   ebccfgd,r4

        addi    r4,0,pb7cr
        mtdcr   ebccfga,r4
        addis   r4,0,0xF031            ; BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),
        ori     r4,r4,0x8000            ; BW=0x0(8 bits)
        mtdcr   ebccfgd,r4

        cmpi    cr0,0,r9,0x0 		; check if I cache was off when we
					; started 
        bne     ..ebc_done		; if it was on, leave on
        addis   r4,r0,0x0000		; if it was off, disable
        mticcr  r4                     ; restore iccr
        isync

..ebc_done:
	nop				; pass2 DCR errata #8
        blr

        .type  ext_bus_cntlr_init,@function
        .size  ext_bus_cntlr_init,.-ext_bus_cntlr_init


#------------------------------------------------------------------------
# Interrupt related functions begin here.
#------------------------------------------------------------------------

#------------------------------------------------------------------------
# Function: system call handler
# Description: Handles context swicth
#------------------------------------------------------------------------
    .text
    .align 2
    .globl  sc_vect

sc_vect:
    bl    OSCtxSw

    .type sc_vect,@function
    .size sc_vect,.-sc_vect

#------------------------------------------------------------------------
# Function: timer handler
# Description: Handles periodic timer
#------------------------------------------------------------------------
    .text
    .align 2
    .globl  timer_vect

timer_vect:
# clear this interrupt.
    mftsr   r3
    mttsr   r3
# invoke the handler.
    bl    interrupt_save_registers
    bl    OSTimeTick
    bl    interrupt_restore_registers 
    isync
    rfi

    .type timer_vect,@function
    .size timer_vect,.-timer_vect


#------------------------------------------------------------------------
# Function: External interrupt handler
# Description: Handles all external interrupts
#------------------------------------------------------------------------
    .text
    .align 2
    .globl  ext_vect

ext_vect:
    bl    interrupt_save_registers
    bl    external_interrupt
    bl    interrupt_restore_registers 
    isync
    rfi


    .type ext_vect,@function
    .size ext_vect,.-ext_vect


#************************************************************************
#   Install a vector                                                    *
#                                                                       *
#   CALL BY:    void set_vector(addr, handler, type, enable_mask        *
#                        long enable_mask);                             *
#                                                                       *
#               uint32    addr;         address of vector to install    *
#               void(*)() handler;      address of handler              *
#               sint32    type;         type of vector to install       *
#               	zero = VT_DIRECT - "handler" is actually vector     *
#                       code and is copied to the specified vector      *
#                                                                       *
#               	10 = VT_INTR - Interrupt exception handler, link    *
#						to it rather than copy lcoally                  *
#                                                                       *
#               uint32    enable_mask;   bit mask to "or" w/ the MSR    *
#                                        *after* SRR0/1 are saved.      *
#               This can be used to quickly re-enable other             *
#               types of exceptions.                                    *
#                                                                       *
#   AT EXIT:    The vector is installed                                 *
#                                                                       *
#************************************************************************

        .text
        .align 2
        .globl  set_vector
#
set_vector:
        stw     r4, V_HANDLER(r3)       # Store handler address
        stw     r6, V_ENABLE_MASK(r3)   # Store bit mask for MSR
#
#------------------------------------------------------------------------
# Load the address of the vector code to copy into r5                   *
#------------------------------------------------------------------------
#
        rlwinm  r8, r5, 16, 16, 31      # number of bytes of code for VT_DIRECT
        rlwinm. r5, r5,  2, 16, 31      # r5: Offset in TC.VECTORS
        bne     NotDirect
#
        cmpwi   r8, 0x0                 # number of instructions to copy
        bne     DirectLen
        li      r8, 0x40
DirectLen:
        mr      r5, r4                  # Code to copy is "handler"
        b       Ready
#
NotDirect:
        li      r8, V_ENDCODE/4         # r8: # instructions to copy
        lis     r6, TC.VECTORS@ha
        addi    r6, r6, TC.VECTORS@l    # r6-> TC.VECTORS
        add     r6, r6, r5              # r6-> TC.VECTORS[type]
        lwz     r5, 0(r6)               # r5-> vector code to copy
#
#------------------------------------------------------------------------
# Now copy the vector code                                              *
#------------------------------------------------------------------------
#