crt0.s
来自「IBM PowerPC 405 在DiabData开发环境下的ucosII移植代」· S 代码 · 共 815 行 · 第 1/3 页
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#------------------------------------------------------------------------------+## This source code has been made available to you by IBM on an AS-IS# basis. Anyone receiving this source is licensed under IBM# copyrights to use it in any way he or she deems fit, including# copying it, modifying it, compiling it, and redistributing it either# with or without modifications. No license under IBM patents or# patent applications is to be implied by the copyright license.## Any user of this software should understand that IBM cannot provide# technical support for this software and will not be responsible for# any consequences resulting from the use of this software.## Any person who transfers this source code or any derivative work# must include the IBM copyright notice, this paragraph, and the# preceding two paragraphs in the transferred software.## COPYRIGHT I B M CORPORATION 1995# LICENSED MATERIAL - PROGRAM PROPERTY OF I B M#-------------------------------------------------------------------------------#-------------------------------------------------------------------------------# File Name: crt0.s# Function: Startup code for Walnut board.# # Change Activity-# # Date Description of Change # --------- --------------------- # 19-Jul-01 IBM code from Metaware compiler to Diab.# 01-Aug-01 Added vector handling mechanisms. #------------------------------------------------------------------------------- .include "p405.inc" .include "board.inc" .file "crt0.s"#---------------------------------------------------------------------# forward declarations#--------------------------------------------------------------------- .globl set_vector # setup an interrupt vector .globl interrupt_save_registers # save all reg's not already saved .globl interrupt_restore_registers # restore reg's and then rfi#------------------------------------------------------------------# RESET_ENTRY. (0xfffffffc). When the 405 resets, this is the# location where the first instruction is executed. #------------------------------------------------------------------ .org RESET_ENTRY .global reset_entryreset_entry: b _start .text .align 2#------------------------------------------------------------------# START OF BOOT CODE.#------------------------------------------------------------------ .text .globl _start .align 2 addi r0,r0,0 _start: addis r11,r0,__SP_INIT@ha # Initialize stack pointer r1 to addi r1,r11,__SP_INIT@l # value in linker command file. addis r13,r0,_SDA_BASE_@ha # Initialize r13 to sdata base addi r13,r13,_SDA_BASE_@l # (provided by linker). addis r2,r0,_SDA2_BASE_@ha # Initialize r2 to sdata2 base addi r2,r2,_SDA2_BASE_@l # (provided by linker). addi r0,r0,0 # Clear r0. stwu r0,-64(r1) # Terminate stack. #--------------------------------------------------------------------- # Setup initial value of MSR. #--------------------------------------------------------------------- addis r4,0,0x00000000@h ori r4,r4,0x00000000@l mtmsr r4 #--------------------------------------------------------------------- # invalidate icache. #--------------------------------------------------------------------- iccci r0,r0 # for 405, iccci invalidates the #--------------------------------------------------------------------- # invalidate dcache #--------------------------------------------------------------------- addi r6,0,0x0000 # clear GPR 6 addi r7,r0, 128 # do loop for # of dcache lines # NOTE: dccci invalidates both mtctr r7 # ways in the D cache..dcloop1: dccci 0,r6 # invalidate line addi r6,r6, 32 # bump to next line bdnz ..dcloop1 #---------------------------------------------------------------------- # Turn off cache for all regions, for now. #---------------------------------------------------------------------- addis r4,r0, CACHE_DISABLED@h # inst cache ori r4,r4, CACHE_DISABLED@l mticcr r4 isync addis r4,r0, CACHE_DISABLED@h # data cache ori r4,r4, CACHE_DISABLED@l mtdccr r4 isync #----------------------------------------------------------------------- # Initialize the External Bus Controller for external peripherals #----------------------------------------------------------------------- bl ext_bus_cntlr_init #----------------------------------------------------------------------- # Initialize the Control 0 register for UART control. # Set UART1 for CTS/RTS and set the UART0 and UART1 external # clock enable to use the external serial clock instead of an # internally derived clock. Set the FPGA control reg for UART1 to # select CTS/RTS. #----------------------------------------------------------------------- addis r3,r0,0x0000 ; set CTS/RTS for UART1 and set ext ori r3,r3,0x10C0 ; clock for UART0 and UART1 mfdcr r4,chcr0 ; read CNTRL0 or r3,r3,r4 ; read-modify-write mtdcr chcr0,r3 ; set CNTRL0 addis r4,r0,FPGA_BRDC@h ori r4,r4,FPGA_BRDC@l lbz r3,0(r4) ; get FPGA board control reg eieio ori r3,r3,0x01 ; set UART1 control to select CTS/RTS stb r3,0(r4) #----------------------------------------------------------------------- # Initialise SPRs #----------------------------------------------------------------------- addi r4,r0,0x0000 mtsgr r4 #no guarded memory mtsler r4 #all memory is in big endian style mtspr su0r,r4 #no storage compression mtesr r4 #clear Exception Syndrome Reg mtxer r4 #clear Fixed-Point Exception Reg addis r4,r0,VECTOR_BASE@h #set exception vector prefix ori r4,r4,VECTOR_BASE@l mtevpr r4 #Vector table address addi r4,r0,0xFFFF #set r4 to 0xFFFFFFFF (status in the mtdbsr r4 #dbsr is cleared by setting bits to 1) #clear/reset the dbsr #----------------------------------------------------------------------- # Initialise Timer #----------------------------------------------------------------------- # reset TBL & TBH addis r4,0,0x0000 # set DC_EN=1 ori r4,r4,0x0000 mttbl r4 # reset lower 32 bit mttbu r4 # reset upper 32 bit # timer control reg init addis r4,0,0x0440 # Wdog period is 2^29 clocks, no watchdog reset ori r4,r4,0x0000 # wdog and fit intr. disabled. pit intr enabled. mttcr r4 #----------------------------------------------------------------------- # Initialise SDRAM's DCR (Indirect) #----------------------------------------------------------------------- bl sdram_init #----------------------------------------------------------------------- # Jump to C ... #----------------------------------------------------------------------- bl main ..stop: b ..stop#-----------------------------------------------------------------------------# Function: sdram_init# Description: Configures SDRAM memory banks.#----------------------------------------------------------------------------- .text .align 2 .globl sdram_initsdram_init: mflr r31 addi r4,0,mem_mb0cf mtdcr memcfga,r4 addis r4,0,SDRAM_BNK0_CF@h ori r4,r4,SDRAM_BNK0_CF@l mtdcr memcfgd,r4 addi r4,0,mem_mb1cf mtdcr memcfga,r4 addis r4,0,SDRAM_BNK1_CF@h ori r4,r4,SDRAM_BNK1_CF@l mtdcr memcfgd,r4 addi r4,0,mem_mb2cf mtdcr memcfga,r4 addis r4,0,SDRAM_BNK2_CF@h ori r4,r4,SDRAM_BNK2_CF@l mtdcr memcfgd,r4 addi r4,0,mem_mb3cf mtdcr memcfga,r4 addis r4,0,SDRAM_BNK3_CF@h ori r4,r4,SDRAM_BNK3_CF@l mtdcr memcfgd,r4 #------------------------------------------------------------------- # Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. # To set the appropriate timings, we need to know the SDRAM speed. # We can use the PLB speed since the SDRAM speed is the same as # the PLB speed. The PLB speed is the FBK divider times the # 405GP reference clock, which on the Walnut board is 33Mhz. # Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is # 100Mhz; if FBK is 3, SDRAM is 133Mhz. # NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and # maybe 133Mhz. #------------------------------------------------------------------- addis r6,0,0x0086 # SDTR1 value for 100Mhz ori r6,r6,0x400D addis r7,0,0x05F0 # RTR value for 100Mhz..sdram_ok: #------------------------------------------------------------------- # Set SDTR1 #------------------------------------------------------------------- addi r4,0,mem_sdtr1 mtdcr memcfga,r4 mtdcr memcfgd,r6 #------------------------------------------------------------------- # Set RTR #------------------------------------------------------------------- addi r4,0,mem_rtr mtdcr memcfga,r4 mtdcr memcfgd,r7 #------------------------------------------------------------------- # Delay to ensure 200usec have elapsed since reset. Assume worst # case that the core is running 200Mhz: # 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles #------------------------------------------------------------------- addis r3,0,0x0000 ori r3,r3,0xA000 # ensure 200usec have passed since reset mtctr r3..spinlp2: bdnz ..spinlp2 # spin loop #------------------------------------------------------------------- # Set memory controller options reg, MCOPT1. #------------------------------------------------------------------- addi r4,0,mem_mcopt1 mtdcr memcfga,r4 addis r4,0,SDRAM_MCOPT1@h ori r4,r4,SDRAM_MCOPT1@l mtdcr memcfgd,r4 #------------------------------------------------------------------- # Delay to ensure 10msec have elapsed since reset. This is # required for the MPC952 to stabalize. Assume worst # case that the core is running 200Mhz: # 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles # This delay should occur before accessing SDRAM. #-------------------------------------------------------------------⌨️ 快捷键说明
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