📄 mcf5206e.h
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#define mcf5206e_UART_UMR2_TXRTS (0x20)
#define mcf5206e_UART_UMR2_TXCTS (0x10)
#define mcf5206e_UART_UMR2_SB3 (0x08)
#define mcf5206e_UART_UMR2_SB2 (0x04)
#define mcf5206e_UART_UMR2_SB1 (0x02)
#define mcf5206e_UART_UMR2_SB0 (0x01)
#define mcf5206e_UART_UMR2_STOP_BITS(a) ((a)&0x0f) /* Stop Bit Length */
#define mcf5206e_UART_UMR2_CM_NORMAL (0x00)
#define mcf5206e_UART_UMR2_CM_ECHO (0x40)
#define mcf5206e_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define mcf5206e_UART_UMR2_CM_REMOTE_LOOP (0xC0)
#define mcf5206e_UART_UMR2_STOP_BITS_1 (0x07)
#define mcf5206e_UART_UMR2_STOP_BITS_15 (0x08)
#define mcf5206e_UART_UMR2_STOP_BITS_2 (0x0F)
#define mcf5206e_UART_USR_RB (0x80)
#define mcf5206e_UART_USR_FE (0x40)
#define mcf5206e_UART_USR_PE (0x20)
#define mcf5206e_UART_USR_OE (0x10)
#define mcf5206e_UART_USR_TXEMP (0x08)
#define mcf5206e_UART_USR_TXRDY (0x04)
#define mcf5206e_UART_USR_FFULL (0x02)
#define mcf5206e_UART_USR_RXRDY (0x01)
#define mcf5206e_UART_UCSR_RCS3 (0x80)
#define mcf5206e_UART_UCSR_RCS2 (0x40)
#define mcf5206e_UART_UCSR_RCS1 (0x20)
#define mcf5206e_UART_UCSR_RCS0 (0x10)
#define mcf5206e_UART_UCSR_TCS3 (0x08)
#define mcf5206e_UART_UCSR_TCS2 (0x04)
#define mcf5206e_UART_UCSR_TCS1 (0x02)
#define mcf5206e_UART_UCSR_TCS0 (0x01)
#define mcf5206e_UART_UCSR_RX_TIMER (0xD0)
#define mcf5206e_UART_UCSR_RX_16EXT (0xE0)
#define mcf5206e_UART_UCSR_RX_1EXT (0xF0)
#define mcf5206e_UART_UCSR_TX_TIMER (0x0D)
#define mcf5206e_UART_UCSR_TX_16EXT (0x0E)
#define mcf5206e_UART_UCSR_TX_1EXT (0x0F)
#define mcf5206e_UART_UCSR_RCS(a) (((a)&0x0f)<<4)
#define mcf5206e_UART_UCSR_TCS(a) ((a)&0x0f)
#define mcf5206e_UART_UCR_MISC2 (0x40)
#define mcf5206e_UART_UCR_MISC1 (0x20)
#define mcf5206e_UART_UCR_MISC0 (0x10)
#define mcf5206e_UART_UCR_TC1 (0x08)
#define mcf5206e_UART_UCR_TC0 (0x04)
#define mcf5206e_UART_UCR_RC1 (0x02)
#define mcf5206e_UART_UCR_RC0 (0x01)
#define mcf5206e_UART_UCR_NONE (0x00)
#define mcf5206e_UART_UCR_STOP_BREAK (0x70)
#define mcf5206e_UART_UCR_START_BREAK (0x60)
#define mcf5206e_UART_UCR_RESET_BKCHGINT (0x50)
#define mcf5206e_UART_UCR_RESET_ERROR (0x40)
#define mcf5206e_UART_UCR_RESET_TX (0x30)
#define mcf5206e_UART_UCR_RESET_RX (0x20)
#define mcf5206e_UART_UCR_RESET_MR (0x10)
#define mcf5206e_UART_UCR_TX_DISABLED (0x08)
#define mcf5206e_UART_UCR_TX_ENABLED (0x04)
#define mcf5206e_UART_UCR_RX_DISABLED (0x02)
#define mcf5206e_UART_UCR_RX_ENABLED (0x01)
#define mcf5206e_UART_UIPCR_COS (0x10)
#define mcf5206e_UART_UIPCR_CTS (0x01)
#define mcf5206e_UART_UACR_BRG (0x80)
#define mcf5206e_UART_UACR_CTMS_TIMER (0x60)
#define mcf5206e_UART_UACR_IEC (0x01)
#define mcf5206e_UART_UISR_COS (0x80)
#define mcf5206e_UART_UISR_DB (0x04)
#define mcf5206e_UART_UISR_RXRDY (0x02)
#define mcf5206e_UART_UISR_TXRDY (0x01)
#define mcf5206e_UART_UIMR_COS (0x80)
#define mcf5206e_UART_UIMR_DB (0x04)
#define mcf5206e_UART_UIMR_FFULL (0x02)
#define mcf5206e_UART_UIMR_TXRDY (0x01)
#define mcf5206e_UART_UIP_CTS (0x01)
#define mcf5206e_UART_UOP1_RTS (0x01)
#define mcf5206e_UART_UOP0_RTS (0x01)
/***********************************************************************/
/*
* M-Bus Module, MBUS
*/
#define mcf5206e_MBUS_MADR (0x01E0)
#define mcf5206e_MBUS_MFDR (0x01E4)
#define mcf5206e_MBUS_MBCR (0x01E8)
#define mcf5206e_MBUS_MBSR (0x01EC)
#define mcf5206e_MBUS_MBDR (0x01F0)
/* Read access macros for general use */
#define mcf5206e_RD_MBUS_MADR(IMMP) mcf5206e_iord(IMMP,mcf5206e_MBUS_MADR,8)
#define mcf5206e_RD_MBUS_MFDR(IMMP) mcf5206e_iord(IMMP,mcf5206e_MBUS_MFDR,8)
#define mcf5206e_RD_MBUS_MBCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_MBUS_MBCR,8)
#define mcf5206e_RD_MBUS_MBSR(IMMP) mcf5206e_iord(IMMP,mcf5206e_MBUS_MBSR,8)
#define mcf5206e_RD_MBUS_MBDR(IMMP) mcf5206e_iord(IMMP,mcf5206e_MBUS_MBDR,8)
/* Write access macros for general use */
#define mcf5206e_WR_MBUS_MADR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_MBUS_MADR,8,DATA)
#define mcf5206e_WR_MBUS_MFDR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_MBUS_MFDR,8,DATA)
#define mcf5206e_WR_MBUS_MBCR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_MBUS_MBCR,8,DATA)
#define mcf5206e_WR_MBUS_MBSR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_MBUS_MBSR,8,DATA)
#define mcf5206e_WR_MBUS_MBDR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_MBUS_MBDR,8,DATA)
#if 1
typedef volatile struct
{
uint8 reserved1[0x1E0];
uint8 MADR;
uint8 reserved2;
uint8 reserved3;
uint8 reserved4;
uint8 MFDR;
uint8 reserved5;
uint8 reserved6;
uint8 reserved7;
uint8 MBCR;
uint8 reserved8;
uint8 reserved9;
uint8 reserved10;
uint8 MBSR;
uint8 reserved11;
uint8 reserved12;
uint8 reserved13;
uint8 MBDR;
} mcf5206e_MBUS;
#endif
#define mcf5206e_MBUS_MADR_ADDR(a) ((a)&0xFE)
#define mcf5206e_MBUS_MFDR_MBC(a) ((a)&0x3F)
#define mcf5206e_MBUS_MBCR_MEN (0x80)
#define mcf5206e_MBUS_MBCR_MIEN (0x40)
#define mcf5206e_MBUS_MBCR_MSTA (0x20)
#define mcf5206e_MBUS_MBCR_MTX (0x10)
#define mcf5206e_MBUS_MBCR_TXAK (0x08)
#define mcf5206e_MBUS_MBCR_RSTA (0x04)
#define mcf5206e_MBUS_MBSR_mcf (0x80)
#define mcf5206e_MBUS_MBSR_MAAS (0x40)
#define mcf5206e_MBUS_MBSR_MBB (0x20)
#define mcf5206e_MBUS_MBSR_MAL (0x10)
#define mcf5206e_MBUS_MBSR_SRW (0x04)
#define mcf5206e_MBUS_MBSR_MIF (0x02)
#define mcf5206e_MBUS_MBSR_RXAK (0x01)
/***********************************************************************/
/*
* Timer Module, TIMER
*/
#define mcf5206e_TIMER1_TMR (0x0100)
#define mcf5206e_TIMER1_TRR (0x0104)
#define mcf5206e_TIMER1_TCR (0x0108)
#define mcf5206e_TIMER1_TCN (0x010C)
#define mcf5206e_TIMER1_TER (0x0111)
#define mcf5206e_TIMER2_TMR (0x0120)
#define mcf5206e_TIMER2_TRR (0x0124)
#define mcf5206e_TIMER2_TCR (0x0128)
#define mcf5206e_TIMER2_TCN (0x012C)
#define mcf5206e_TIMER2_TER (0x0131)
/* Read access macros for general use */
#define mcf5206e_RD_TIMER1_TMR(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER1_TMR,16)
#define mcf5206e_RD_TIMER1_TRR(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER1_TRR,16)
#define mcf5206e_RD_TIMER1_TCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER1_TCR,16)
#define mcf5206e_RD_TIMER1_TCN(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER1_TCN,16)
#define mcf5206e_RD_TIMER1_TER(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER1_TER,8)
#define mcf5206e_RD_TIMER2_TMR(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER2_TMR,16)
#define mcf5206e_RD_TIMER2_TRR(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER2_TRR,16)
#define mcf5206e_RD_TIMER2_TCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER2_TCR,16)
#define mcf5206e_RD_TIMER2_TCN(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER2_TCN,16)
#define mcf5206e_RD_TIMER2_TER(IMMP) mcf5206e_iord(IMMP,mcf5206e_TIMER2_TER,8)
/* Write access macros for general use */
#define mcf5206e_WR_TIMER1_TMR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_TIMER1_TMR,16,DATA)
#define mcf5206e_WR_TIMER1_TRR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_TIMER1_TRR,16,DATA)
#define mcf5206e_WR_TIMER1_TCN(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_TIMER1_TCN,16,DATA)
#define mcf5206e_WR_TIMER1_TER(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_TIMER1_TER,8,DATA)
#define mcf5206e_WR_TIMER2_TMR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_TIMER2_TMR,16,DATA)
#define mcf5206e_WR_TIMER2_TRR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_TIMER2_TRR,16,DATA)
#define mcf5206e_WR_TIMER2_TCN(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_TIMER2_TCN,16,DATA)
#define mcf5206e_WR_TIMER2_TER(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_TIMER2_TER,8,DATA)
#if 1
typedef volatile struct
{
uint8 reserved0[0x100];
uint16 TMR1;
uint16 reserved1;
uint16 TRR1;
uint16 reserved2;
uint16 TCR1;
uint16 reserved3;
uint16 TCN1;
uint16 reserved4;
uint8 reserved5;
uint8 TER1;
uint32 reserved6;
uint32 reserved7;
uint32 reserved8;
uint16 reserved9;
uint16 TMR2;
uint16 reserved10;
uint16 TRR2;
uint16 reserved11;
uint16 TCR2;
uint16 reserved12;
uint16 TCN2;
uint16 reserved13;
uint8 reserved14;
uint8 TER2;
} mcf5206e_TIMER;
#endif
#define mcf5206e_TIMER_TMR_PS(a) (((a)&0x00FF)<<8)
#define mcf5206e_TIMER_TMR_CE_ANY (0x00C0)
#define mcf5206e_TIMER_TMR_CE_RISE (0x0080)
#define mcf5206e_TIMER_TMR_CE_FALL (0x0040)
#define mcf5206e_TIMER_TMR_CE_NONE (0x0000)
#define mcf5206e_TIMER_TMR_OM (0x0020)
#define mcf5206e_TIMER_TMR_ORI (0x0010)
#define mcf5206e_TIMER_TMR_FRR (0x0008)
#define mcf5206e_TIMER_TMR_CLK_TIN (0x0006)
#define mcf5206e_TIMER_TMR_CLK_DIV16 (0x0004)
#define mcf5206e_TIMER_TMR_CLK_MSCLK (0x0002)
#define mcf5206e_TIMER_TMR_CLK_STOP (0x0000)
#define mcf5206e_TIMER_TMR_RST (0x0001)
#define mcf5206e_TIMER_TER_REF (0x02)
#define mcf5206e_TIMER_TER_CAP (0x01)
/***********************************************************************/
/*
* DMA Module, DMA
*/
#define mcf5206e_DMA0_SAR (0x0200)
#define mcf5206e_DMA0_DAR (0x0204)
#define mcf5206e_DMA0_DCR (0x0208)
#define mcf5206e_DMA0_BCR (0x020C)
#define mcf5206e_DMA0_DSR (0x0210)
#define mcf5206e_DMA0_DIVR (0x0214)
#define mcf5206e_DMA1_SAR (0x0240)
#define mcf5206e_DMA1_DAR (0x0244)
#define mcf5206e_DMA1_DCR (0x024C)
#define mcf5206e_DMA1_BCR (0x0250)
#define mcf5206e_DMA1_DSR (0x0250)
#define mcf5206e_DMA1_DIVR (0x0254)
/* Read access macros for general use */
#define mcf5206e_RD_DMA0_SAR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA0_SAR,32)
#define mcf5206e_RD_DMA0_DAR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA0_DAR,32)
#define mcf5206e_RD_DMA0_DCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA0_DCR,16)
#define mcf5206e_RD_DMA0_BCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA0_BCR,16)
#define mcf5206e_RD_DMA0_DSR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA0_DSR,8)
#define mcf5206e_RD_DMA0_DIVR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA0_DIVR,8)
#define mcf5206e_RD_DMA1_SAR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA1_SAR,32)
#define mcf5206e_RD_DMA1_DAR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA1_DAR,32)
#define mcf5206e_RD_DMA1_DCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA1_DCR,16)
#define mcf5206e_RD_DMA1_BCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA1_BCR,16)
#define mcf5206e_RD_DMA1_DSR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA1_DSR,8)
#define mcf5206e_RD_DMA1_DIVR(IMMP) mcf5206e_iord(IMMP,mcf5206e_DMA1_DIVR,8)
/* Write access macros for general use */
#define mcf5206e_WR_DMA0_SAR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA0_SAR,32,DATA)
#define mcf5206e_WR_DMA0_DAR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA0_DAR,32,DATA)
#define mcf5206e_WR_DMA0_DCR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA0_DCR,16,DATA)
#define mcf5206e_WR_DMA0_BCR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA0_BCR,16,DATA)
#define mcf5206e_WR_DMA0_DSR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA0_DSR,8,DATA)
#define mcf5206e_WR_DMA0_DIVR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA0_DIVR,8,DATA)
#define mcf5206e_WR_DMA1_SAR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA1_SAR,32,DATA)
#define mcf5206e_WR_DMA1_DAR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA1_DAR,32,DATA)
#define mcf5206e_WR_DMA1_DCR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA1_DCR,16,DATA)
#define mcf5206e_WR_DMA1_BCR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA1_BCR,16,DATA)
#define mcf5206e_WR_DMA1_DSR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA1_DSR,8,DATA)
#define mcf5206e_WR_DMA1_DIVR(IMMP,DATA) mcf5206e_iowr(IMMP,mcf5206e_DMA1_DIVR,8,DATA)
#if 1
typedef volatile struct
{
uint8 reserved1[0x200];
uint32 SAR0;
uint32 DAR0;
uint16 DCR0;
uint16 reserved2;
uint16 BCR0;
uint16 reserved3;
uint8 DSR0;
uint8 reserved4;
uint16 reserved5;
uint8 DIVR0;
uint8 reserved6;
uint16 reserved7;
uint32 reserved8[0xa];
uint32 SAR1;
uint32 DAR1;
uint16 DCR1;
uint16 reserved9;
uint16 BCR1;
uint16 reserved10;
uint8 DSR1;
uint8 reserved11;
uint16 reserved12;
uint8 DIVR1;
} mcf5206e_DMA;
#endif
#define mcf5206e_DMA_DCR_INT (0x8000) /* Interrupt on Completion */
#define mcf5206e_DMA_DCR_EEXT (0x4000) /* Enable External Request */
#define mcf5206e_DMA_DCR_CS (0x2000) /* Cycle Steal */
#define mcf5206e_DMA_DCR_AA (0x1000) /* Auto Align */
#define mcf5206e_DMA_DCR_BWC_DMA (0x0000) /* Bandwidth: DMA Priority */
#define mcf5206e_DMA_DCR_BWC_512 (0x0200) /* Bandwidth: 512 Bytes */
#define mcf5206e_DMA_DCR_BWC_1024 (0x0400) /* Bandwidth: 1024 Bytes */
#define mcf5206e_DMA_DCR_BWC_2048 (0x0600) /* Bandwidth: 2048 Bytes */
#define mcf5206e_DMA_DCR_BWC_4096 (0x0800) /* Bandwidth: 4096 Bytes */
#define mcf5206e_DMA_DCR_BWC_8192 (0x0a00) /* Bandwidth: 8192 Bytes */
#define mcf5206e_DMA_DCR_BWC_16384 (0x0c00) /* Bandwidth: 16384 Bytes */
#define mcf5206e_DMA_DCR_BWC_32768 (0x0e00) /* Bandwidth: 32768 Bytes */
#define mcf5206e_DMA_DCR_SAA (0x0100) /* Single Address Access */
#define mcf5206e_DMA_DCR_SRW (0x0080) /* Forces MRW Signal High */
#define mcf5206e_DMA_DCR_SINC (0x0040) /* Source Increment */
#define mcf5206e_DMA_DCR_SSIZE_LONG (0x0000) /* Source Size: Longword */
#define mcf5206e_DMA_DCR_SSIZE_BYTE (0x0010) /* Source Size: Byte */
#define mcf5206e_DMA_DCR_SSIZE_WORD (0x0020) /* Source Size: Word */
#define mcf5206e_DMA_DCR_SSIZE_LINE (0x0030) /* Source Size: Line */
#define mcf5206e_DMA_DCR_DINC (0x0008) /* Destination Increment */
#define mcf5206e_DMA_DCR_DSIZE_LONG (0x0000) /* Destination Size: Longword */
#define mcf5206e_DMA_DCR_DSIZE_BYTE (0x0002) /* Destination Size: Byte */
#define mcf5206e_DMA_DCR_DSIZE_WORD (0x0004) /* Destination Size: Word */
#define mcf5206e_DMA_DCR_START (0x0001) /* Start Transfer */
#define mcf5206e_DMA_DSR_CE (0x40) /* Configuration Error */
#define mcf5206e_DMA_DSR_BES (0x20) /* Bus Error on Source */
#define mcf5206e_DMA_DSR_BED (0x10) /* Bus Error on Destination */
#define mcf5206e_DMA_DSR_REQ (0x04) /* Request */
#define mcf5206e_DMA_DSR_BSY (0x02) /* Busy */
#define mcf5206e_DMA_DSR_DONE (0x01) /* Transaction Done */
/***********************************************************************/
#if 1
/*
* Here we put the modules together. An example access for the UART mode
* register would be: (assuming we have a pointer to the IMM):
*
* imm->uart1.UMR
*/
typedef volatile union
{
mcf5206e_SIM sim;
mcf5206e_PP pp;
mcf5206e_UART1 uart1;
mcf5206e_UART2 uart2;
mcf5206e_TIMER timer;
mcf5206e_CS cs;
mcf5206e_DRAMC dramc;
mcf5206e_MBUS mbus;
mcf5206e_DMA dma;
} mcf5206e_IMM;
#endif
/***********************************************************************/
extern volatile PVECTORTABLE pEVT;
extern volatile mcf5206e_IMM *pIMM;
#endif /* _CPU_mcf5206e_H */
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