📄 mcf5206e.h
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* DRAM Controller Module, DRAMC
*/
/* Offsets of the registers from the MBAR */
#define mcf5206e_DRAMC_DCRR (0x0046)
#define mcf5206e_DRAMC_DCTR (0x004A)
#define mcf5206e_DRAMC_DCAR0 (0x004C)
#define mcf5206e_DRAMC_DCMR0 (0x0050)
#define mcf5206e_DRAMC_DCCR0 (0x0057)
#define mcf5206e_DRAMC_DCAR1 (0x0058)
#define mcf5206e_DRAMC_DCMR1 (0x005C)
#define mcf5206e_DRAMC_DCCR1 (0x0063)
/* Read access macros for general use */
#define mcf5206e_RD_DRAMC_DCRR(IMMP) \
mcf5206e_iord(IMMP,mcf5206e_DRAMC_DCRR,16)
#define mcf5206e_RD_DRAMC_DCTR(IMMP) \
mcf5206e_iord(IMMP,mcf5206e_DRAMC_DCTR,16)
#define mcf5206e_RD_DRAMC_DCAR0(IMMP) \
mcf5206e_iord(IMMP,mcf5206e_DRAMC_DCAR0,16)
#define mcf5206e_RD_DRAMC_DCMR0(IMMP) \
mcf5206e_iord(IMMP,mcf5206e_DRAMC_DCMR0,32)
#define mcf5206e_RD_DRAMC_DCCR0(IMMP) \
mcf5206e_iord(IMMP,mcf5206e_DRAMC_DCCR0,8)
#define mcf5206e_RD_DRAMC_DCAR1(IMMP) \
mcf5206e_iord(IMMP,mcf5206e_DRAMC_DCAR1,16)
#define mcf5206e_RD_DRAMC_DCMR1(IMMP) \
mcf5206e_iord(IMMP,mcf5206e_DRAMC_DCMR1,32)
#define mcf5206e_RD_DRAMC_DCCR1(IMMP) \
mcf5206e_iord(IMMP,mcf5206e_DRAMC_DCCR1,8)
/* Write access macros for general use */
#define mcf5206e_WR_DRAMC_DCRR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_DRAMC_DCRR,16,DATA)
#define mcf5206e_WR_DRAMC_DCTR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_DRAMC_DCTR,16,DATA)
#define mcf5206e_WR_DRAMC_DCAR0(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_DRAMC_DCAR0,16,DATA)
#define mcf5206e_WR_DRAMC_DCMR0(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_DRAMC_DCMR0,32,DATA)
#define mcf5206e_WR_DRAMC_DCCR0(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_DRAMC_DCCR0,8,DATA)
#define mcf5206e_WR_DRAMC_DCAR1(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_DRAMC_DCAR1,16,DATA)
#define mcf5206e_WR_DRAMC_DCMR1(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_DRAMC_DCMR1,32,DATA)
#define mcf5206e_WR_DRAMC_DCCR1(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_DRAMC_DCCR1,8,DATA)
#if 1
typedef volatile struct
{
uint16 reserved1[0x23];
uint16 DCRR;
uint16 reserved2;
uint16 DCTR;
uint16 DCAR0;
uint16 reserved4;
uint32 DCMR0;
uint8 reserved5[3];
uint8 DCCR0;
uint16 DCAR1;
uint16 reserved6;
uint32 DCMR1;
uint8 reserved7[3];
uint8 DCCR1;
} mcf5206e_DRAMC;
#endif
#define mcf5206e_DRAMC_DCRR_RC(a) ((a)&0x0FFF)
#define mcf5206e_DRAMC_DCTR_DAEM (0x8000)
#define mcf5206e_DRAMC_DCTR_EDO (0x4000)
#define mcf5206e_DRAMC_DCTR_RCD (0x1000)
#define mcf5206e_DRAMC_DCTR_RSH_1 (0x0000)
#define mcf5206e_DRAMC_DCTR_RSH_2 (0x0200)
#define mcf5206e_DRAMC_DCTR_RSH_3 (0x0400)
#define mcf5206e_DRAMC_DCTR_CRP_15 (0x0000)
#define mcf5206e_DRAMC_DCTR_CRP_25 (0x0020)
#define mcf5206e_DRAMC_DCTR_CRP_35 (0x0040)
#define mcf5206e_DRAMC_DCTR_CAS (0x0008)
#define mcf5206e_DRAMC_DCTR_CP (0x0002)
#define mcf5206e_DRAMC_DCTR_CSR (0x0001)
#define mcf5206e_DRAMC_DCAR_BASE(a) (((a)&0xFFFE0000)>>16)
#define mcf5206e_DRAMC_DCMR_MASK_128M (0x07FE0000)
#define mcf5206e_DRAMC_DCMR_MASK_64M (0x03FE0000)
#define mcf5206e_DRAMC_DCMR_MASK_32M (0x01FE0000)
#define mcf5206e_DRAMC_DCMR_MASK_16M (0x00FE0000)
#define mcf5206e_DRAMC_DCMR_MASK_8M (0x007E0000)
#define mcf5206e_DRAMC_DCMR_MASK_4M (0x003E0000)
#define mcf5206e_DRAMC_DCMR_MASK_2M (0x001E0000)
#define mcf5206e_DRAMC_DCMR_MASK_1M (0x000E0000)
#define mcf5206e_DRAMC_DCMR_MASK_512K (0x00060000)
#define mcf5206e_DRAMC_DCMR_MASK_256K (0x00020000)
#define mcf5206e_DRAMC_DCMR_MASK_128K (0x00000000)
#define mcf5206e_DRAMC_DCMR_SC (0x00000010)
#define mcf5206e_DRAMC_DCMR_SD (0x00000008)
#define mcf5206e_DRAMC_DCMR_UC (0x00000004)
#define mcf5206e_DRAMC_DCMR_UD (0x00000002)
#define mcf5206e_DRAMC_DCCR_PS_32 (0x00)
#define mcf5206e_DRAMC_DCCR_PS_16 (0x80)
#define mcf5206e_DRAMC_DCCR_PS_8 (0x40)
#define mcf5206e_DRAMC_DCCR_PS_MASK (0xC0)
#define mcf5206e_DRAMC_DCCR_BPS_512B (0x00)
#define mcf5206e_DRAMC_DCCR_BPS_1K (0x10)
#define mcf5206e_DRAMC_DCCR_BPS_2K (0x20)
#define mcf5206e_DRAMC_DCCR_PM_NORMAL (0x00)
#define mcf5206e_DRAMC_DCCR_PM_BURSTPAGE (0x04)
#define mcf5206e_DRAMC_DCCR_PM_FASTPAGE (0x0C)
#define mcf5206e_DRAMC_DCCR_WR (0x02)
#define mcf5206e_DRAMC_DCCR_RD (0x01)
/***********************************************************************/
/*
* UART Module, UART
*/
#define mcf5206e_UART1_UMR (0x0140)
#define mcf5206e_UART1_USR (0x0144)
#define mcf5206e_UART1_UCSR (0x0144)
#define mcf5206e_UART1_UCR (0x0148)
#define mcf5206e_UART1_URB (0x014C)
#define mcf5206e_UART1_UTB (0x014C)
#define mcf5206e_UART1_UIPCR (0x0150)
#define mcf5206e_UART1_UACR (0x0150)
#define mcf5206e_UART1_UISR (0x0154)
#define mcf5206e_UART1_UIMR (0x0154)
#define mcf5206e_UART1_UBG1 (0x0158)
#define mcf5206e_UART1_UBG2 (0x015C)
#define mcf5206e_UART1_UIVR (0x0170)
#define mcf5206e_UART1_UIP (0x0174)
#define mcf5206e_UART1_UOP1 (0x0178)
#define mcf5206e_UART1_UOP0 (0x017C)
#define mcf5206e_UART2_UMR (0x0180)
#define mcf5206e_UART2_USR (0x0184)
#define mcf5206e_UART2_UCSR (0x0184)
#define mcf5206e_UART2_UCR (0x0188)
#define mcf5206e_UART2_URB (0x018C)
#define mcf5206e_UART2_UTB (0x018C)
#define mcf5206e_UART2_UIPCR (0x0190)
#define mcf5206e_UART2_UACR (0x0190)
#define mcf5206e_UART2_UISR (0x0194)
#define mcf5206e_UART2_UIMR (0x0194)
#define mcf5206e_UART2_UBG1 (0x0198)
#define mcf5206e_UART2_UBG2 (0x019C)
#define mcf5206e_UART2_UIVR (0x01B0)
#define mcf5206e_UART2_UIP (0x01B4)
#define mcf5206e_UART2_UOP1 (0x01B8)
#define mcf5206e_UART2_UOP0 (0x01BC)
/* Read access macros for general use */
#define mcf5206e_RD_UART1_UMR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART1_UMR,8)
#define mcf5206e_RD_UART1_USR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART1_USR,8)
#define mcf5206e_RD_UART1_URB(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART1_URB,8)
#define mcf5206e_RD_UART1_UIPCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART1_UIPCR,8)
#define mcf5206e_RD_UART1_UISR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART1_UISR,8)
#define mcf5206e_RD_UART1_UBG1(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART1_UBG1,8)
#define mcf5206e_RD_UART1_UBG2(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART1_UBG2,8)
#define mcf5206e_RD_UART1_UIVR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART1_UIVR,8)
#define mcf5206e_RD_UART1_UIP(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART1_UIP,8)
#define mcf5206e_RD_UART2_UMR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART2_UMR,8)
#define mcf5206e_RD_UART2_USR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART2_USR,8)
#define mcf5206e_RD_UART2_URB(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART2_URB,8)
#define mcf5206e_RD_UART2_UIPCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART2_UIPCR,8)
#define mcf5206e_RD_UART2_UISR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART2_UISR,8)
#define mcf5206e_RD_UART2_UBG1(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART2_UBG1,8)
#define mcf5206e_RD_UART2_UBG2(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART2_UBG2,8)
#define mcf5206e_RD_UART2_UIVR(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART2_UIVR,8)
#define mcf5206e_RD_UART2_UIP(IMMP) mcf5206e_iord(IMMP,mcf5206e_UART2_UIP,8)
/* Write access macros for general use */
#define mcf5206e_WR_UART1_UMR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UMR,8,DATA)
#define mcf5206e_WR_UART1_UCSR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UCSR,8,DATA)
#define mcf5206e_WR_UART1_UCR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UCR,8,DATA)
#define mcf5206e_WR_UART1_UTB(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UTB,8,DATA)
#define mcf5206e_WR_UART1_UACR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UACR,8,DATA)
#define mcf5206e_WR_UART1_UIMR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UIMR,8,DATA)
#define mcf5206e_WR_UART1_UBG1(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UBG1,8,DATA)
#define mcf5206e_WR_UART1_UBG2(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UBG2,8,DATA)
#define mcf5206e_WR_UART1_UIVR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UIVR,8,DATA)
#define mcf5206e_WR_UART1_UOP1(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UOP1,8,DATA)
#define mcf5206e_WR_UART1_UOP0(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART1_UOP0,8,DATA)
#define mcf5206e_WR_UART2_UMR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UMR,8,DATA)
#define mcf5206e_WR_UART2_UCSR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UCSR,8,DATA)
#define mcf5206e_WR_UART2_UCR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UCR,8,DATA)
#define mcf5206e_WR_UART2_UTB(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UTB,8,DATA)
#define mcf5206e_WR_UART2_UACR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UACR,8,DATA)
#define mcf5206e_WR_UART2_UIMR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UIMR,8,DATA)
#define mcf5206e_WR_UART2_UBG1(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UBG1,8,DATA)
#define mcf5206e_WR_UART2_UBG2(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UBG2,8,DATA)
#define mcf5206e_WR_UART2_UIVR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UIVR,8,DATA)
#define mcf5206e_WR_UART2_UOP1(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UOP1,8,DATA)
#define mcf5206e_WR_UART2_UOP0(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_UART2_UOP0,8,DATA)
#if 1
typedef volatile struct
{
uint8 reserved1[0x140];
uint8 UMR;
#define UMR1 UMR // Mode Register (w)
#define UMR2 UMR // Receive Buffer (w)
uint8 reserved2;
uint8 reserved3;
uint8 reserved4;
uint8 USR;
#define UCSR USR // Clock-Select Register (w)
uint8 reserved5;
uint8 reserved6;
uint8 reserved7;
uint8 UCR;
uint8 reserved8;
uint8 reserved9;
uint8 reserved10;
uint8 UBUF;
#define URB UBUF // Receive Buffer (r)
#define UTB UBUF // Transmit Buffer (w)
uint8 reserved11;
uint8 reserved12;
uint8 reserved13;
uint8 UIPCR;
#define UACR UIPCR // Aux Control Reg (w)
uint8 reserved14;
uint8 reserved15;
uint8 reserved16;
uint8 UIR;
#define UIMR UIR // Interrupt Mask Reg (w)
#define UISR UIR // Interrupt Status Reg (r)
uint8 reserved17;
uint8 reserved18;
uint8 reserved19;
uint8 UBG1;
uint8 reserved20;
uint8 reserved21;
uint8 reserved22;
uint8 UBG2;
uint8 reserved23; // do this for proper byte alignment
uint8 reserved24[0x12];
uint8 UIVR;
uint8 reserved25;
uint8 reserved26;
uint8 reserved27;
uint8 UIP;
uint8 reserved28;
uint8 reserved29;
uint8 reserved30;
uint8 UOP1;
uint8 reserved31;
uint8 reserved32;
uint8 reserved33;
uint8 UOP0;
} mcf5206e_UART1;
typedef volatile struct
{
uint8 reserved1[0x180];
uint8 UMR;
uint8 reserved2;
uint8 reserved3;
uint8 reserved4;
uint8 USR;
uint8 reserved5;
uint8 reserved6;
uint8 reserved7;
uint8 UCR;
uint8 reserved8;
uint8 reserved9;
uint8 reserved10;
uint8 UBUF;
uint8 reserved11;
uint8 reserved12;
uint8 reserved13;
uint8 UIPCR;
uint8 reserved14;
uint8 reserved15;
uint8 reserved16;
uint8 UIR;
uint8 reserved17;
uint8 reserved18;
uint8 reserved19;
uint8 UBG1;
uint8 reserved20;
uint8 reserved21;
uint8 reserved22;
uint8 UBG2;
uint8 reserved23; // do this for proper byte alignment
uint8 reserved24[0x12];
uint8 UIVR;
uint8 reserved25;
uint8 reserved26;
uint8 reserved27;
uint8 UIP;
uint8 reserved28;
uint8 reserved29;
uint8 reserved30;
uint8 UOP1;
uint8 reserved31;
uint8 reserved32;
uint8 reserved33;
uint8 UOP0;
} mcf5206e_UART2;
// generic UART struct for either port
typedef volatile struct
{
uint8 UMR;
uint8 reserved2;
uint8 reserved3;
uint8 reserved4;
uint8 USR;
uint8 reserved5;
uint8 reserved6;
uint8 reserved7;
uint8 UCR;
uint8 reserved8;
uint8 reserved9;
uint8 reserved10;
uint8 UBUF;
uint8 reserved11;
uint8 reserved12;
uint8 reserved13;
uint8 UIPCR;
uint8 reserved14;
uint8 reserved15;
uint8 reserved16;
uint8 UIR;
uint8 reserved17;
uint8 reserved18;
uint8 reserved19;
uint8 UBG1;
uint8 reserved20;
uint8 reserved21;
uint8 reserved22;
uint8 UBG2;
uint8 reserved23; // do this for proper byte alignment
uint8 reserved24[0x12];
uint8 UIVR;
uint8 reserved25;
uint8 reserved26;
uint8 reserved27;
uint8 UIP;
uint8 reserved28;
uint8 reserved29;
uint8 reserved30;
uint8 UOP1;
uint8 reserved31;
uint8 reserved32;
uint8 reserved33;
uint8 UOP0;
} mcf5206e_UART;
#endif
#define mcf5206e_UART_UMR1_RXRTS (0x80)
#define mcf5206e_UART_UMR1_RXIRQ (0x40)
#define mcf5206e_UART_UMR1_ERR (0x20)
#define mcf5206e_UART_UMR1_PM1 (0x10)
#define mcf5206e_UART_UMR1_PM0 (0x08)
#define mcf5206e_UART_UMR1_PMT (0x04)
#define mcf5206e_UART_UMR1_BC1 (0x02)
#define mcf5206e_UART_UMR1_BC0 (0x01)
#define mcf5206e_UART_UMR1_PM_MULTI_ADDR (0x1C)
#define mcf5206e_UART_UMR1_PM_MULTI_DATA (0x18)
#define mcf5206e_UART_UMR1_PM_NONE (0x10)
#define mcf5206e_UART_UMR1_PM_FORCE_HI (0x0C)
#define mcf5206e_UART_UMR1_PM_FORCE_LO (0x08)
#define mcf5206e_UART_UMR1_PM_ODD (0x04)
#define mcf5206e_UART_UMR1_PM_EVEN (0x00)
#define mcf5206e_UART_UMR1_BC_5 (0x00)
#define mcf5206e_UART_UMR1_BC_6 (0x01)
#define mcf5206e_UART_UMR1_BC_7 (0x02)
#define mcf5206e_UART_UMR1_BC_8 (0x03)
#define mcf5206e_UART_UMR2_CM1 (0x80)
#define mcf5206e_UART_UMR2_CM0 (0x40)
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