📄 mcf5206e.h
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/*
* File: mcf5206e.h
* Purpose: mcf5206e definitions
*
*/
#ifndef _CPU_mcf5206e_H
#define _CPU_mcf5206e_H
#ifdef __MWERKS__
/* Turn off C++ so functions can be called from assembly */
#pragma cplusplus off
/* Turn off optimizations to prevent inadvertent optimizing of critical code */
#pragma optimization_level 0
#endif
/***********************************************************************/
/*
* Misc. Defines
*/
#ifdef FALSE
#undef FALSE
#endif
#define FALSE (0)
#ifdef TRUE
#undef TRUE
#endif
#define TRUE (1)
#ifdef NULL
#undef NULL
#endif
#define NULL (0)
/***********************************************************************/
/*
* The basic data types
*/
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef signed char int8; /* 8 bits */
typedef signed short int int16; /* 16 bits */
typedef signed long int int32; /* 32 bits */
typedef unsigned char BOOL; /* true/false */
/***********************************************************************/
/*
* Common M68K & ColdFire definitions
*/
#define ADDRESS uint32
#define INSTRUCTION uint16
#define ILLEGAL 0x4AFC
#define CPU_WORD_SIZE 16
/***********************************************************************/
/*
* Routines and macros for accessing Input/Output devices
*/
#define cpu_iord_8(ADDR) *((volatile uint8 *)(ADDR))
#define cpu_iord_16(ADDR) *((volatile uint16 *)(ADDR))
#define cpu_iord_32(ADDR) *((volatile uint32 *)(ADDR))
#define cpu_iowr_8(ADDR,DATA) *((volatile uint8 *)(ADDR)) = (DATA)
#define cpu_iowr_16(ADDR,DATA) *((volatile uint16 *)(ADDR)) = (DATA)
#define cpu_iowr_32(ADDR,DATA) *((volatile uint32 *)(ADDR)) = (DATA)
/***********************************************************************/
#define MCF5200_SR_T (0x8000)
#define MCF5200_SR_S (0x2000)
#define MCF5200_SR_M (0x1000)
#define MCF5200_SR_IPL (0x0700)
#define MCF5200_SR_IPL_0 (0x0000)
#define MCF5200_SR_IPL_1 (0x0100)
#define MCF5200_SR_IPL_2 (0x0200)
#define MCF5200_SR_IPL_3 (0x0300)
#define MCF5200_SR_IPL_4 (0x0400)
#define MCF5200_SR_IPL_5 (0x0500)
#define MCF5200_SR_IPL_6 (0x0600)
#define MCF5200_SR_IPL_7 (0x0700)
#define MCF5200_SR_X (0x0010)
#define MCF5200_SR_N (0x0008)
#define MCF5200_SR_Z (0x0004)
#define MCF5200_SR_V (0x0002)
#define MCF5200_SR_C (0x0001)
/* Exception Vector Table memory map structure */
typedef struct
{
uint32 ISP; /* Initial Stack Pointer (000-003) */
uint32 IPC; /* Inital Program Counter (004-007) */
uint32 AccErr; /* Access Error (008-00B) */
uint32 AddErr; /* Address Error (00C-00F) */
uint32 IllInst; /* Illegal Instruction (010-013) */
uint32 Pack01[3]; /* Reserved (014-01F) */
uint32 PrivVio; /* Privilege Violation (020-023) */
uint32 Trace; /* Trace (024-027) */
uint32 ULAO; /* Unimplemented line-a opcode (028-02B) */
uint32 ULFO; /* Unimplemented line-f opcode (02C-02F) */
uint32 DbgInt; /* Debug Interrupt (030-033) */
uint32 Pack02[1]; /* Reserved (034-037) */
uint32 FE; /* Format Error (038-03B) */
uint32 UI; /* Uninitialized Interrupt (03C-03F) */
uint32 Pack03[8]; /* Reserved (040-05F) */
uint32 SI; /* Spurious Interrupt (060-063) */
uint32 Level[7]; /* Autovectored interrupts - 7 Levels (064-07F) */
uint32 Trap[16]; /* Trap #0-15 instructions (080-0BF) */
uint32 Pack04[16]; /* Reserved (0C0-0FF) */
uint32 UserDef[192]; /* User-defined Interrupts (100-3FF) */
} VECTORTABLE, * PVECTORTABLE;
typedef enum {
EVT_LEVEL_1 = 0,
EVT_LEVEL_2,
EVT_LEVEL_3,
EVT_LEVEL_4,
EVT_LEVEL_5,
EVT_LEVEL_6,
EVT_LEVEL_7
} EVT_INT_LEVELS;
#define AVEC_VECT_NUM(level) (25 + (level-1))
/***********************************************************************/
/*
* The ColdFire family of processors has a simplified exception stack
* frame that looks like the following:
*
* 3322222222221111 111111
* 1098765432109876 5432109876543210
* 8 +----------------+----------------+
* | Program Counter |
* 4 +----------------+----------------+
* |FS/Fmt/Vector/FS| SR |
* SP --> 0 +----------------+----------------+
*
* The stack self-aligns to a 4-byte boundary at an exception, with
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
* (SP += 0,1,2,3 bytes).
*/
#define MCF5200_RD_SF_FORMAT(PTR) \
((*((uint16 *)(PTR)) >> 12) & 0x00FF)
#define MCF5200_RD_SF_VECTOR(PTR) \
((*((uint16 *)(PTR)) >> 2) & 0x00FF)
#define MCF5200_RD_SF_FS(PTR) \
( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
#define MCF5200_SF_SR(PTR) *((uint16 *)(PTR)+1)
#define MCF5200_SF_PC(PTR) *((uint32 *)(PTR)+1)
#if 0
typedef struct
{
uint16 SR;
uint16 FS_FMT_VECTOR_FS;
uint32 PC;
} MCF5200_STACK_FRAME;
#endif
/* Extract the Format Status information from the Exception Stack Frame */
#define ERROR_ESF_GET_FS(a) (uint8) (((a)&0x00030000)>>16 | \
((a)&0x0C000000)>>24)
#define ESF_PC_MASK_WORD 0x0003FFFF
/* Extract the Exception Vector from the Exception Stack Frame */
#define ERROR_ESF_GET_VECTOR(a) (uint8) (((a)&0x00FF0000)>>18)
typedef struct _StackFrame {
/*
** Registers, stack pointer, and exception type.
** We pushed these items at the start of exception handling.
*/
uint32 d0;
uint32 d1;
uint32 d2;
uint32 d3;
uint32 d4;
uint32 d5;
uint32 d6;
uint32 d7;
uint32 a0;
uint32 a1;
uint32 a2;
uint32 a3;
uint32 a4;
uint32 a5;
uint32 a6;
uint32 sp;
/*
** The coldfire exception frame
*/
union _Frame {
struct _Fvsr {
uint16 Format:4;
uint16 FaultStatus32:2;
uint16 Vector:8;
uint16 FaultStatus10:2;
uint16 sr;
} Fvsr;
uint32 FvsrWord;
} Frame;
uint32 pc;
} STACK_FRAME;
/***********************************************************************/
/*
* Function prototypes for ColdFire processors
*
* MCF5200/D: Only VBR valid
* MCF5202: Only VBR, CACR, ACR0, ACR1 valid
* MCF5204: All valid
* MCF5206: All valid
* MCF5206e: All valid
*/
void
mcf5206e_wr_vbr (uint32);
void
mcf5206e_wr_cacr (uint32);
void
mcf5206e_wr_acr0 (uint32);
void
mcf5206e_wr_acr1 (uint32);
void
mcf5206e_wr_rambar (uint32);
void
mcf5206e_wr_mbar (uint32);
/***********************************************************************/
/*
* Cache and Access Control Register routines and defintions
*/
#define mcf5206e_CACR_CENB (0x80000000)
#define mcf5206e_CACR_CFRZ (0x08000000)
#define mcf5206e_CACR_CINV (0x01000000)
#define mcf5206e_CACR_CMOD (0x00000200)
#define mcf5206e_CACR_CWRP (0x00000020)
#define mcf5206e_CACR_CLNF_00 (0x00000000)
#define mcf5206e_CACR_CLNF_01 (0x00000001)
#define mcf5206e_CACR_CLNF_10 (0x00000002)
#define mcf5206e_ACR_BASE(a) ((a)&0xFF000000)
#define mcf5206e_ACR_MASK(a) (((a)&0xFF000000) >> 8)
#define mcf5206e_ACR_EN (0x00008000)
#define mcf5206e_ACR_S_USER (0x00000000)
#define mcf5206e_ACR_S_SUPER (0x00002000)
#define mcf5206e_ACR_S_IGNORE (0x00006000)
#define mcf5206e_ACR_ENIB (0x00000080)
#define mcf5206e_ACR_CM (0x00000040)
#define mcf5206e_ACR_WP (0x00000004)
#define mcf5206e_SRAMBAR_BASE(a) ((a)&0xFFFFFE00)
#define mcf5206e_SRAMBAR_WP (0x00000100)
#define mcf5206e_SRAMBAR_AS_CI (0x00000080)
#define mcf5206e_SRAMBAR_AS_SC (0x00000040)
#define mcf5206e_SRAMBAR_AS_SD (0x00000020)
#define mcf5206e_SRAMBAR_AS_UC (0x00000004)
#define mcf5206e_SRAMBAR_AS_UD (0x00000002)
#define mcf5206e_SRAMBAR_V (0x00000001)
#define mcf5206e_MBAR_BASE(a) ((a)&0xFFFFFC00)
#define mcf5206e_MBAR_SC (0x00000010)
#define mcf5206e_MBAR_SD (0x00000008)
#define mcf5206e_MBAR_UC (0x00000004)
#define mcf5206e_MBAR_UD (0x00000002)
#define mcf5206e_MBAR_V (0x00000001)
/***********************************************************************/
/*
* Macro for computing address of on-chip peripheral registers
*/
#define mcf5206e_addr(IMMP,OFFSET) ((void *)&((uint8 *)IMMP)[OFFSET])
/*
* Macros for accessing the on-chip I/O resources
*/
#define mcf5206e_iord(IMMP,OFFSET,SIZE) \
*(volatile uint ## SIZE *)(mcf5206e_addr(IMMP,OFFSET))
#define mcf5206e_iowr(IMMP,OFFSET,SIZE,DATA) \
*(volatile uint ## SIZE *)(mcf5206e_addr(IMMP,OFFSET)) = (DATA)
/***********************************************************************/
/*
* System Integration Modules, SIM
*/
/* Offsets of the registers from the MBAR */
#define mcf5206e_SIM_SIMR (0x0003)
#define mcf5206e_SIM_ICR1 (0x0014)
#define mcf5206e_SIM_ICR2 (0x0015)
#define mcf5206e_SIM_ICR3 (0x0016)
#define mcf5206e_SIM_ICR4 (0x0017)
#define mcf5206e_SIM_ICR5 (0x0018)
#define mcf5206e_SIM_ICR6 (0x0019)
#define mcf5206e_SIM_ICR7 (0x001A)
#define mcf5206e_SIM_ICR8 (0x001B)
#define mcf5206e_SIM_ICR9 (0x001C)
#define mcf5206e_SIM_ICR10 (0x001D)
#define mcf5206e_SIM_ICR11 (0x001E)
#define mcf5206e_SIM_ICR12 (0x001F)
#define mcf5206e_SIM_ICR13 (0x0020)
#define mcf5206e_SIM_IMR (0x0036)
#define mcf5206e_SIM_IPR (0x003A)
#define mcf5206e_SIM_RSR (0x0040)
#define mcf5206e_SIM_SYPCR (0x0041)
#define mcf5206e_SIM_SWIVR (0x0042)
#define mcf5206e_SIM_SWSR (0x0043)
#define mcf5206e_SIM_PAR (0x00CA)
/* Read access macros for general use */
#define mcf5206e_RD_SIM_SIMR(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_SIMR,8)
#define mcf5206e_RD_SIM_ICR1(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR1,8)
#define mcf5206e_RD_SIM_ICR2(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR2,8)
#define mcf5206e_RD_SIM_ICR3(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR3,8)
#define mcf5206e_RD_SIM_ICR4(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR4,8)
#define mcf5206e_RD_SIM_ICR5(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR5,8)
#define mcf5206e_RD_SIM_ICR6(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR6,8)
#define mcf5206e_RD_SIM_ICR7(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR7,8)
#define mcf5206e_RD_SIM_ICR8(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR8,8)
#define mcf5206e_RD_SIM_ICR9(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR9,8)
#define mcf5206e_RD_SIM_ICR10(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR10,8)
#define mcf5206e_RD_SIM_ICR11(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR11,8)
#define mcf5206e_RD_SIM_ICR12(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR12,8)
#define mcf5206e_RD_SIM_ICR13(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_ICR13,8)
#define mcf5206e_RD_SIM_IMR(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_IMR,16)
#define mcf5206e_RD_SIM_IPR(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_IPR,16)
#define mcf5206e_RD_SIM_RSR(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_RSR,8)
#define mcf5206e_RD_SIM_SYPCR(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_SYPCR,8)
#define mcf5206e_RD_SIM_SWIVR(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_SWIVR,8)
#define mcf5206e_RD_SIM_PAR(IMMP) mcf5206e_iord(IMMP,mcf5206e_SIM_PAR,16)
/* Write access macros for general use */
#define mcf5206e_WR_SIM_SIMR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_SIMR,8,DATA)
#define mcf5206e_WR_SIM_ICR1(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR1,8,DATA)
#define mcf5206e_WR_SIM_ICR2(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR2,8,DATA)
#define mcf5206e_WR_SIM_ICR3(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR3,8,DATA)
#define mcf5206e_WR_SIM_ICR4(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR4,8,DATA)
#define mcf5206e_WR_SIM_ICR5(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR5,8,DATA)
#define mcf5206e_WR_SIM_ICR6(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR6,8,DATA)
#define mcf5206e_WR_SIM_ICR7(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR7,8,DATA)
#define mcf5206e_WR_SIM_ICR8(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR8,8,DATA)
#define mcf5206e_WR_SIM_ICR9(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR9,8,DATA)
#define mcf5206e_WR_SIM_ICR10(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR10,8,DATA)
#define mcf5206e_WR_SIM_ICR11(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR11,8,DATA)
#define mcf5206e_WR_SIM_ICR12(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR12,8,DATA)
#define mcf5206e_WR_SIM_ICR13(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_ICR13,8,DATA)
#define mcf5206e_WR_SIM_IMR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_IMR,16,DATA)
#define mcf5206e_WR_SIM_RSR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_RSR,8,DATA)
#define mcf5206e_WR_SIM_SYPCR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_SYPCR,8,DATA)
#define mcf5206e_WR_SIM_SWIVR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_SWIVR,8,DATA)
#define mcf5206e_WR_SIM_SWSR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_SWSR,8,DATA)
#define mcf5206e_WR_SIM_PAR(IMMP,DATA) \
mcf5206e_iowr(IMMP,mcf5206e_SIM_PAR,16,DATA)
#if 1
typedef volatile struct
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