tim_a.c

摩托罗拉MMC2107在ucosII的移植代码

/**********************************************************************/
/* File: tim_a.c        File containing API functions                 */
/*                      for the TIM_A                                 */
/*                                                                    */
/* Design Reference:  Doc. Name                       Version         */
/*                    ---------------------------     -------         */
/*                    TIM_A Level 1 Service           1.0             */
/*                    Functional Design Specification                 */
/*                                                                    */
/*     (C) Copyright Motorola Inc, 2000.  All rights reserved.        */
/*                                                                    */
/*     $RCSfile: tim_a.h,v $                                          */
/*     $Revision: 1.0 $                                               */
/*     $Date: 2000/06/23 20:22:21 $                                   */
/*     $Author: Dmitry Shvarts $                                      */
/**********************************************************************/

#include "tim_a.h"

/*--------------------------------------------------------------------*/
/* API's                                                         */
/*--------------------------------------------------------------------*/

TIM_A_ReturnCode_t TIM_A_Init_f(
                  pTIM_A_t                        TIMPtr,
                   TIM_A_TIMEnable_t              TIMEnable,
                   TIM_A_FastClearEnable_t        FastClearEnable,
                   TIM_A_InterruptEnable_t        InterruptEnable,
                   TIM_A_PullupInputEnable_t      InputPullupEnable,
                   TIM_A_DrvReducedOutputEnable_t DriveReductionEnable,
                   TIM_A_CounterResetOn3Enable_t  CntResetOn3Enable,
                   TIM_A_PreScalarSelect_t        PreScalarSelect )
{
	/*            Register     Offset Length Value             BitName */
	/* =============================================================== */
	SET_REG_BITS( TIMPtr->TIMSCR1, 7, 1, TIMEnable            ); /* TIMEN */
	SET_REG_BITS( TIMPtr->TIMSCR1, 4, 1, FastClearEnable      ); /* TFFCA */

	SET_REG_BITS( TIMPtr->TIMSCR2, 7, 1, InterruptEnable      ); /* TOI   */
	SET_REG_BITS( TIMPtr->TIMSCR2, 5, 1, InputPullupEnable    ); /* PUPT  */
	SET_REG_BITS( TIMPtr->TIMSCR2, 4, 1, DriveReductionEnable ); /* RDPT  */
	SET_REG_BITS( TIMPtr->TIMSCR2, 3, 1, CntResetOn3Enable    ); /* TCRE  */

	/* clear old PRE and set the new one */
	SET_REG_BITS( TIMPtr->TIMSCR2, 0, 3, PreScalarSelect      ); /* PR */

    return (TIM_A_ERR_NONE);
}

TIM_A_ReturnCode_t TIM_A_ConfigChannelInputCapture_f(
                  pTIM_A_t                        TIMPtr,
				   TIM_A_Channel_t                Ch,
                   TIM_A_InputCaptureEdge_t       InputCaptureEdge,
                   TIM_A_InterruptEnable_t        InterruptEnable )
{
	/*            Register    Offset Length Value              BitName */
	/* =============================================================== */
	/* 1) Clear the pin's IOS bit in TIMIOS */
	SET_REG_BITS( TIMPtr->TIMIOS , Ch, 1, 0                   ); /* IOSx */
	/* 2) Clear the pin's DDR bit in TIMDDR */
	SET_REG_BITS( TIMPtr->TIMDDR , Ch, 1, 0                   ); /* DDRTx */
	
	/* *) Enable/Disable Intterupt */
	SET_REG_BITS( TIMPtr->TIMIE  , Ch, 1, InterruptEnable     ); /* CxI */
	/* *) Set edge for Input Capture */
	SET_REG_BITS( TIMPtr->TIMCTL2, Ch*2, 2, InputCaptureEdge  ); /* EDGxB,EDGxA */

    return (TIM_A_ERR_NONE);
}

TIM_A_ReturnCode_t TIM_A_ConfigChannelOuputCompare_f(
                  pTIM_A_t                        TIMPtr,
				   TIM_A_Channel_t                Ch,
                   TIM_A_OutputCompare3Mask_t     OutputCompare3Mask,
                   TIM_A_ToggleOnOverflow_t       ToggleOnOverflow,
                   TIM_A_OutputAction_t           OutputAction,
                   TIM_A_InterruptEnable_t        InterruptEnable,
                   UINT16                         CompareValue )
{
	/*            Register     Offset Length Value             BitName */
	/* =============================================================== */
	/* 1) Set the pin's IOS bit in TIMIOS */
	SET_REG_BITS( TIMPtr->TIMIOS , Ch, 1, 1                   ); /* IOSx */
	/* 2) Write the output compare value to TIMCxH/L */
	TIMPtr->TIMC[ Ch ] = CompareValue;
	/* 3) Clear the pin's DDR bit in TIMDDR */
	SET_REG_BITS( TIMPtr->TIMDDR , Ch, 1, 0                   ); /* DDRTx */
	/* 4) Write to the OMx/OLx bits in TIMCTL1 to select the output action */
	SET_REG_BITS( TIMPtr->TIMCTL1, Ch*2, 2, OutputAction      ); /* OMx,OLx */
	
	/*            Register     Offset Length Value             BitName */
	/* =============================================================== */
	/* Whether to drive data bit on channel 3 compare or not */
	SET_REG_BITS( TIMPtr->TIMOC3M, Ch, 1, OutputCompare3Mask  ); /* OC3DMx */
	/* *) Enable/Disable Intterupt */
	SET_REG_BITS( TIMPtr->TIMIE  , Ch, 1, InterruptEnable     ); /* CxI */
	/* *) Enable/Disable toggle on overflow */
	SET_REG_BITS( TIMPtr->TIMTOV , Ch, 1, ToggleOnOverflow    ); /* TOVx */
	
    return (TIM_A_ERR_NONE);
}

    /***********************************************************
    Be aware! Compare value 0x0000 has no effect when channel is set
    to be toggled on timer overflow. The reason for this is that
    both of them happen when counter rolls over from 0xFFFF to
    0x0000. As a result, two events create a collision, trying
    to change a signal in opposite directions. Timer overflow takes
    over Output Compare.
    ***********************************************************/

TIM_A_ReturnCode_t TIM_A_SetCompareValue_f(
                  pTIM_A_t                        TIMPtr,
                   TIM_A_Channel_t                Ch,
                   UINT16                         CompareValue )
{
	TIMPtr->TIMC[ Ch ] = CompareValue;

    return (TIM_A_ERR_NONE);
}

TIM_A_ReturnCode_t TIM_A_SetOutputAction_f(
                  pTIM_A_t                        TIMPtr,
                   TIM_A_Channel_t                Ch,
                   TIM_A_OutputAction_t           OutputAction )
{
	/*            Register     Offset Length Value             BitName */
	/* =============================================================== */
	SET_REG_BITS( TIMPtr->TIMCTL1, Ch*2, 2, OutputAction      ); /* OMx,OLx */

    return (TIM_A_ERR_NONE);
}

TIM_A_ReturnCode_t TIM_A_ForceOutput_f(
                  pTIM_A_t                        TIMPtr,
                   TIM_A_Channel_t                Ch )
{
	/*            Register     Offset Length Value             BitName */
	/* =============================================================== */
    SET_REG_BITS( TIMPtr->TIMCFORC, Ch, 1, 1                  ); /* FOCx */

    return (TIM_A_ERR_NONE);
}

TIM_A_ReturnCode_t TIM_A_SetRegister_f(
                  pTIM_A_t                       TIMPtr,
                   TIM_A_Register_t              RegisterSelect,
                   UINT16                        RegisterValue )
{

    return (TIM_A_ERR_NONE);
}

TIM_A_ReturnCode_t TIM_A_GetRegister_f(
                  pTIM_A_t                       TIMPtr,
                  TIM_A_Register_t               TIMRegister,
                  UINT16                         *GetRegisterPtr )
{

    return (TIM_A_ERR_NONE);
}

TIM_A_ReturnCode_t TIM_A_ControlOperation_f(
                  pTIM_A_t                        TIMPtr,
                   TIM_A_TIMEnable_t              TIMEnable )
{
	SET_REG_BITS( TIMPtr->TIMSCR1, 7, 1, TIMEnable            ); /* TIMEN */
    
    return (TIM_A_ERR_NONE);
}

TIM_A_ReturnCode_t TIM_A_ControlInterrupt_f(
                  pTIM_A_t                        TIMPtr,
                   TIM_A_InterruptEnable_t        TIE )
{

    return (TIM_A_ERR_NONE);
}

TIM_A_ReturnCode_t TIM_A_GetStatus_f(
                  pTIM_A_t                        TIMPtr,
                  pTIM_A_Status_t                 GetStatusPtr
                                   );

TIM_A_ReturnCode_t TIM_A_Reset_f(
                  pTIM_A_t                       TIMPtr
                                );