📄 port_a.h
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/*********************************************************************/
/* File: edgeport_b.h */
/* */
/* Purpose: File containing the structures and prototypes for the */
/* Edge Port device driver */
/* */
/* (C) Copyright Motorola Inc, 2000. All rights reserved. */
/* */
/* $RCSfile: port_a.h,v $ */
/* $Revision: 1.1 $ */
/* $Date: 2000/06/23 20:00:09 $ */
/* $Author: csummers $ */
/* */
/*********************************************************************/
#ifndef _PORTS_B_H
#define _PORTS_B_H
#include "mcore.h"
/*-------------------------------------------------------------------*/
/* Enumerations */
/*-------------------------------------------------------------------*/
typedef enum
{
PORT_A_ERR_NONE = 0x0L, /* no error (force long) */
PORT_A_ERR_INVALID_HANDLE, /* Device Handle is NULL */
PORT_A_ERR_INVALID_PIN_NUMBER, /* Pin selection is invalid. */
PORT_A_ERR_INVALID_PORT, /* Port selectio is invalid. */
PORT_A_ERR_INVALID_DATA_VALUE, /* Value written invalid. */
PORT_A_ERR_BAD_RESULT_ADDRESS, /* Result Address is NULL. */
PORT_A_ERR_INVALID_REGISTER, /* Register selection invalid.*/
PORT_A_ERR_INVALID_FUNCTION, /* Function selection invalid.*/
PORT_A_ERR_INVALID_SELECTION /* Selection for pins invalid.*/
} Port_A_ReturnCode_t;
typedef enum{
PORT_A_PORTA,
PORT_A_PORTB,
PORT_A_PORTC,
PORT_A_PORTD,
PORT_A_PORTE,
PORT_A_PORTF,
PORT_A_PORTG,
PORT_A_PORTH,
PORT_A_PORTI,
PORT_A_DDRA, /* Port Data Direction Register A */
PORT_A_DDRB, /* Port Data Direction Register B */
PORT_A_DDRC, /* Port Data Direction Register C */
PORT_A_DDRD, /* Port Data Direction Register D */
PORT_A_DDRE, /* Port Data Direction Register E */
PORT_A_DDRF, /* Port Data Direction Register F */
PORT_A_DDRG, /* Port Data Direction Register G */
PORT_A_DDRH, /* Port Data Direction Register H */
PORT_A_DDRI, /* Port Data Direction Register I */
PORT_A_PORTAP_SETA, /* Port Pin/Set Data Register A */
PORT_A_PORTBP_SETB, /* Port Pin/Set Data Register B */
PORT_A_PORTCP_SETC, /* Port Pin/Set Data Register C */
PORT_A_PORTDP_SETD, /* Port Pin/Set Data Register D */
PORT_A_PORTEP_SETE, /* Port Pin/Set Data Register E */
PORT_A_PORTFP_SETF, /* Port Pin/Set Data Register F */
PORT_A_PORTGP_SETG, /* Port Pin/Set Data Register G */
PORT_A_PORTHP_SETH, /* Port Pin/Set Data Register H */
PORT_A_PORTIP_SETI, /* Port Pin/Set Data Register I */
PORT_A_CLRA, /* Port Clear Output Data Register A*/
PORT_A_CLRB, /* Port Clear Output Data Register B*/
PORT_A_CLRC, /* Port Clear Output Data Register C*/
PORT_A_CLRD, /* Port Clear Output Data Register D*/
PORT_A_CLRE, /* Port Clear Output Data Register E*/
PORT_A_CLRF, /* Port Clear Output Data Register F*/
PORT_A_CLRG, /* Port Clear Output Data Register G*/
PORT_A_CLRH, /* Port Clear Output Data Register H*/
PORT_A_CLRI, /* Port Clear Output Data Register I*/
PORT_A_PCDPAR, /* Port Pin Assignment Register */
PORT_A_PEPAR /* Port Pin Assignment Register */
} Port_A_Register_t;
typedef enum{
PORT_A_DIGITAL_IO, /* Pin configured for digital i/o */
PORT_A_PRIMARY_FUNCTION /* Pin perform primary functions. */
} Port_A_Function_t;
typedef enum{
PORT_A_SHS, /* Pin 7 of PEPAR register. */
PORT_A_TA, /* Pin 6 of PEPAR register. */
PORT_A_TEA, /* Pin 5 of PEPAR register. */
PORT_A_CSE, /* Pin [4:3] of PEPAR register. */
PORT_A_TC, /* Pin [2:0] of PEPAR register. */
PORT_A_PORT_CD /* Pin 7 of PCDPAR register. */
} Port_A_Selection_t;
typedef enum {
PORT_A_PORT_A, /* Port A selection. */
PORT_A_PORT_B, /* Port B selection. */
PORT_A_PORT_C, /* Port C selection. */
PORT_A_PORT_D, /* Port D selection. */
PORT_A_PORT_E, /* Port E selection. */
PORT_A_PORT_F, /* Port F selection. */
PORT_A_PORT_G, /* Port G selection. */
PORT_A_PORT_H, /* Port H selection. */
PORT_A_PORT_I /* Port I selection. */
} Port_A_Port_t;
typedef enum {
PORT_A_PORTPIN_0,
PORT_A_PORTPIN_1,
PORT_A_PORTPIN_2,
PORT_A_PORTPIN_3,
PORT_A_PORTPIN_4,
PORT_A_PORTPIN_5,
PORT_A_PORTPIN_6,
PORT_A_PORTPIN_7
} Port_A_Pin_t;
typedef enum {
PORT_A_CLEAR,
PORT_A_SET
} Port_A_DataVal_t;
typedef struct
{
volatile UINT8 PORTA;
volatile UINT8 PORTB;
volatile UINT8 PORTC;
volatile UINT8 PORTD;
volatile UINT8 PORTE;
volatile UINT8 PORTF;
volatile UINT8 PORTG;
volatile UINT8 PORTH;
volatile UINT8 PORTI;
volatile UINT8 RESERVED0;
volatile UINT8 RESERVED1;
volatile UINT8 RESERVED2;
UINT8 DDRA;
UINT8 DDRB;
UINT8 DDRC;
UINT8 DDRD;
UINT8 DDRE;
UINT8 DDRF;
UINT8 DDRG;
UINT8 DDRH;
UINT8 DDRI;
UINT8 Reserved3;
UINT8 Reserved4;
UINT8 Reserved5;
volatile UINT8 PORTAP_SETA;
volatile UINT8 PORTBP_SETB;
volatile UINT8 PORTCP_SETC;
volatile UINT8 PORTDP_SETD;
volatile UINT8 PORTEP_SETE;
volatile UINT8 PORTFP_SETF;
volatile UINT8 PORTGP_SETG;
volatile UINT8 PORTHP_SETH;
volatile UINT8 PORTIP_SETI;
volatile UINT8 Reserved6;
volatile UINT8 Reserved7;
volatile UINT8 Reserved8;
UINT8 CLRA;
UINT8 CLRB;
UINT8 CLRC;
UINT8 CLRD;
UINT8 CLRE;
UINT8 CLRF;
UINT8 CLRG;
UINT8 CLRH;
UINT8 CLRI;
UINT8 Reserved9;
UINT8 Reserved10;
UINT8 Reserved11;
UINT8 PCDPAR;
UINT8 PEPAR;
} Port_A_t, *pPort_A_t;
/*-------------------------------------------------------------------*/
/* Register Bits & Masks */
/*-------------------------------------------------------------------*/
/* Port Output Data Register A Macro */
#define PORTx_PORTx0_BITNO 0
#define PORTx_PORTx0_MASK (1<<PORTx_PORTx0_BITNO) /*0000 0001 */
#define PORTx_PORTx1_BITNO 1
#define PORTx_PORTx1_MASK (1<<PORTx_PORTx1_BITNO) /*0000 0010 */
#define PORTx_PORTx2_BITNO 2
#define PORTx_PORTx2_MASK (1<<PORTx_PORTx2_BITNO) /*0000 0100 */
#define PORTx_PORTx3_BITNO 3
#define PORTx_PORTx3_MASK (1<<PORTx_PORTx3_BITNO) /*0000 1000 */
#define PORTx_PORTx4_BITNO 4
#define PORTx_PORTx4_MASK (1<<PORTx_PORTx4_BITNO) /*0001 0000 */
#define PORTx_PORTx5_BITNO 5
#define PORTx_PORTx5_MASK (1<<PORTx_PORTx5_BITNO) /*0010 0000 */
#define PORTx_PORTx6_BITNO 6
#define PORTx_PORTx6_MASK (1<<PORTx_PORTx6_BITNO) /*0100 0000 */
#define PORTx_PORTx7_BITNO 7
#define PORTx_PORTx7_MASK (1<<PORTx_PORTx7_BITNO) /*1000 0000 */
#define PORTx_PORTx_BITNO 0
#define PORTx_PORTx_MAX 0xFF
#define PORTx_PORTx_MASK (PORTx_PORTx_MAX<<PORTx_PORTx_BITNO)
#define PORTx_RESET_MASK (0xFF)
/* Port Data Direction Register A Macro */
#define DDRx_DDRx0_BITNO 0
#define DDRx_DDRx0_MASK (1<<DDRx_DDRx0_BITNO) /*0000 0001 */
#define DDRx_DDRx1_BITNO 1
#define DDRx_DDRx1_MASK (1<<DDRx_DDRx1_BITNO) /*0000 0010 */
#define DDRx_DDRx2_BITNO 2
#define DDRx_DDRx2_MASK (1<<DDRx_DDRx2_BITNO) /*0000 0100 */
#define DDRx_DDRx3_BITNO 3
#define DDRx_DDRx3_MASK (1<<DDRx_DDRx3_BITNO) /*0000 1000 */
#define DDRx_DDRx4_BITNO 4
#define DDRx_DDRx4_MASK (1<<DDRx_DDRx4_BITNO) /*0001 0000 */
#define DDRx_DDRx5_BITNO 5
#define DDRx_DDRx5_MASK (1<<DDRx_DDRx5_BITNO) /*0010 0000 */
#define DDRx_DDRx6_BITNO 6
#define DDRx_DDRx6_MASK (1<<DDRx_DDRx6_BITNO) /*0100 0000 */
#define DDRx_DDRx7_BITNO 7
#define DDRx_DDRx7_MASK (1<<DDRx_DDRx7_BITNO) /*1000 0000 */
#define DDRx_DDRx_BITNO 0
#define DDRx_DDRx_MAX 0XFF
#define DDRx_DDRx_MASK (DDRx_DDRx_MAX<<DDRx_DDRx_BITNO)
#define DDRx_RESET_MASK (0x00)
/* Port Pin/Set Data Registers A Macro */
#define PORTxP_SETx_PORTxP0_SETx0_BITNO 0
#define PORTxP_SETx_PORTxP0_SETx0_MASK (1<<PORTxP_SETx_PORTxP0_SETx0_BITNO)
#define PORTxP_SETx_PORTxP1_SETx1_BITNO 1
#define PORTxP_SETx_PORTxP1_SETx1_MASK (1<< PORTxP_SETx_PORTxP1_SETx1_BITNO)
#define PORTxP_SETx_PORTxP2_SETx2_BITNO 2
#define PORTxP_SETx_PORTxP2_SETx2_MASK (1<<PORTxP_SETx_PORTxP2_SETx2_BITNO)
#define PORTxP_SETx_PORTxP3_SETx3_BITNO 3
#define PORTxP_SETx_PORTxP3_SETx3_MASK (1<< PORTxP_SETx_PORTxP3_SETx3_BITNO)
#define PORTxP_SETx_PORTxP4_SETx4_BITNO 4
#define PORTxP_SETx_PORTxP4_SETx4_MASK (1<<PORTxP_SETx_PORTxP4_SETx4_BITNO)
#define PORTxP_SETx_PORTxP5_SETx5_BITNO 5
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