sci_d.h

摩托罗拉MMC2107在ucosII的移植代码

#define SCIBDL_SBR0_BITNO		0
#define SCIBDL_SBR0_MASK		(1 << SCIBDL_SBR0_BITNO)	/* 00000001 */
#define SCIBDL_SBR1_BITNO		1
#define SCIBDL_SBR1_MASK		(1 << SCIBDL_SBR1_BITNO)	/* 00000010 */
#define SCIBDL_SBR2_BITNO		2
#define SCIBDL_SBR2_MASK		(1 << SCIBDL_SBR2_BITNO)	/* 00000100 */
#define SCIBDL_SBR3_BITNO		3
#define SCIBDL_SBR3_MASK		(1 << SCIBDL_SBR3_BITNO)	/* 00001000 */
#define SCIBDL_SBR4_BITNO		4
#define SCIBDL_SBR4_MASK		(1 << SCIBDL_SBR4_BITNO)	/* 00010000 */
#define SCIBDL_SBR5_BITNO		5
#define SCIBDL_SBR5_MASK		(1 << SCIBDL_SBR5_BITNO)	/* 00100000 */
#define SCIBDL_SBR6_BITNO		6
#define SCIBDL_SBR6_MASK		(1 << SCIBDL_SBR6_BITNO)	/* 01000000 */
#define SCIBDL_SBR7_BITNO		7
#define SCIBDL_SBR7_MASK		(1 << SCIBDL_SBR7_BITNO)	/* 10000000 */

#define SCIBDL_SBR_BITNO		0							
#define SCIBDL_SBR_MASK			(0xFF)						/* 11111111 */
#define SCIBDL_RESET_MASK		(1 << SCIBDL_SBR2_BITNO)	/* 00000100 */


#define SCICR1_PT_BITNO			0
#define SCICR1_PT_MASK			(1 << SCICR1_PT_BITNO)		/* 00000001 */
#define SCICR1_PE_BITNO			1
#define SCICR1_PE_MASK			(1 << SCICR1_PE_BITNO)		/* 00000010 */
#define SCICR1_ILT_BITNO		2
#define SCICR1_ILT_MASK			(1 << SCICR1_ILT_BITNO)		/* 00000100 */
#define SCICR1_WAKE_BITNO		3
#define SCICR1_WAKE_MASK		(1 << SCICR1_WAKE_BITNO)	/* 00001000 */
#define SCICR1_M_BITNO			4
#define SCICR1_M_MASK			(1 << SCICR1_M_BITNO)		/* 00010000 */
#define SCICR1_RSRC_BITNO		5
#define SCICR1_RSRC_MASK		(1 << SCICR1_RSRC_BITNO)	/* 00100000 */
#define SCICR1_WOMS_BITNO		6
#define SCICR1_WOMS_MASK		(1 << SCICR1_WOMS_BITNO)	/* 01000000 */
#define SCICR1_LOOPS_BITNO		7
#define SCICR1_LOOPS_MASK		(1 << SCICR1_LOOPS_BITNO)	/* 10000000 */

#define SCICR1_RESET_MASK		(0x00)						/* 00000000 */


#define SCICR2_SBK_BITNO		0
#define SCICR2_SBK_MASK			(1 << SCICR2_SBK_BITNO)		/* 00000001 */
#define SCICR2_RWU_BITNO		1
#define SCICR2_RWU_MASK			(1 << SCICR2_RWU_BITNO)		/* 00000010 */
#define SCICR2_RE_BITNO			2
#define SCICR2_RE_MASK			(1 << SCICR2_RE_BITNO)		/* 00000100 */
#define SCICR2_TE_BITNO			3
#define SCICR2_TE_MASK			(1 << SCICR2_TE_BITNO)		/* 00001000 */
#define SCICR2_ILIE_BITNO		4
#define SCICR2_ILIE_MASK		(1 << SCICR2_ILIE_BITNO)	/* 00010000 */
#define SCICR2_RIE_BITNO		5
#define SCICR2_RIE_MASK			(1 << SCICR2_RIE_BITNO)		/* 00100000 */
#define SCICR2_TCIE_BITNO		6
#define SCICR2_TCIE_MASK		(1 << SCICR2_TCIE_BITNO)	/* 01000000 */
#define SCICR2_TIE_BITNO		7
#define SCICR2_TIE_MASK			(1 << SCICR2_TIE_BITNO)		/* 10000000 */

#define SCICR2_RESET_MASK		(0x00)						/* 00000000 */


#define SCISR1_PF_BITNO			0
#define SCISR1_PF_MASK			(1 << SCISR1_PF_BITNO)		/* 00000001 */
#define SCISR1_FE_BITNO			1
#define SCISR1_FE_MASK			(1 << SCISR1_FE_BITNO)		/* 00000010 */
#define SCISR1_NF_BITNO			2
#define SCISR1_NF_MASK			(1 << SCISR1_NF_BITNO)		/* 00000100 */
#define SCISR1_OR_BITNO			3
#define SCISR1_OR_MASK			(1 << SCISR1_OR_BITNO)		/* 00001000 */
#define SCISR1_IDLE_BITNO		4
#define SCISR1_IDLE_MASK		(1 << SCISR1_IDLE_BITNO)	/* 00010000 */
#define SCISR1_RDRF_BITNO		5
#define SCISR1_RDRF_MASK		(1 << SCISR1_RDRF_BITNO)	/* 00100000 */
#define SCISR1_TC_BITNO			6
#define SCISR1_TC_MASK			(1 << SCISR1_TC_BITNO)		/* 01000000 */
#define SCISR1_TDRE_BITNO		7
#define SCISR1_TDRE_MASK		(1 << SCISR1_TDRE_BITNO)	/* 10000000 */

#define SCISR1_RESET_MASK		(0x00)						/* 00000000 */


#define SCISR2_RAF_BITNO		0
#define SCISR2_RAF_MASK			(1 << SCISR2_RAF_BITNO)		/* 00000001 */

#define SCISR2_RESET_MASK		(0x00)						/* 00000000 */


#define SCIDRH_T8_BITNO			6
#define SCIDRH_T8_MASK			(1 << SCIDRH_T8_BITNO)		/* 01000000 */
#define SCIDRH_R8_BITNO			7
#define SCIDRH_R8_MASK			(1 << SCIDRH_R8_BITNO)		/* 10000000 */

#define SCIDRH_RESET_MASK		(0x00)						/* 00000000 */


#define SCIDRL_T0_BITNO			0
#define SCIDRL_T0_MASK			(1 << SCIDRL_T0_BITNO)		/* 00000001 */
#define SCIDRL_R0_BITNO			0
#define SCIDRL_R0_MASK			(1 << SCIDRL_R0_BITNO)		/* 00000001 */
#define SCIDRL_T1_BITNO			1
#define SCIDRL_T1_MASK			(1 << SCIDRL_T1_BITNO)		/* 00000010 */
#define SCIDRL_R1_BITNO			1
#define SCIDRL_R1_MASK			(1 << SCIDRL_R1_BITNO)		/* 00000010 */
#define SCIDRL_T2_BITNO			2
#define SCIDRL_T2_MASK			(1 << SCIDRL_T2_BITNO)		/* 00000100 */
#define SCIDRL_R2_BITNO			2
#define SCIDRL_R2_MASK			(1 << SCIDRL_R2_BITNO)		/* 00000100 */
#define SCIDRL_T3_BITNO			3
#define SCIDRL_T3_MASK			(1 << SCIDRL_T3_BITNO)		/* 00001000 */
#define SCIDRL_R3_BITNO			3
#define SCIDRL_R3_MASK			(1 << SCIDRL_R3_BITNO)		/* 00001000 */
#define SCIDRL_T4_BITNO			4
#define SCIDRL_T4_MASK			(1 << SCIDRL_T4_BITNO)		/* 00010000 */
#define SCIDRL_R4_BITNO			4
#define SCIDRL_R4_MASK			(1 << SCIDRL_R4_BITNO)		/* 00010000 */
#define SCIDRL_T5_BITNO			5
#define SCIDRL_T5_MASK			(1 << SCIDRL_T5_BITNO)		/* 00100000 */
#define SCIDRL_R5_BITNO			5
#define SCIDRL_R5_MASK			(1 << SCIDRL_R5_BITNO)		/* 00100000 */
#define SCIDRL_T6_BITNO			6
#define SCIDRL_T6_MASK			(1 << SCIDRL_T6_BITNO)		/* 01000000 */
#define SCIDRL_R6_BITNO			6
#define SCIDRL_R6_MASK			(1 << SCIDRL_R6_BITNO)		/* 01000000 */
#define SCIDRL_T7_BITNO			7
#define SCIDRL_T7_MASK			(1 << SCIDRL_T7_BITNO)		/* 10000000 */
#define SCIDRL_R7_BITNO			7
#define SCIDRL_R7_MASK			(1 << SCIDRL_R7_BITNO)		/* 10000000 */

#define SCIDRL_T_MASK			(0xFF)						/* 11111111 */
#define SCIDRL_R_MASK			(0xFF) 						/* 11111111 */

#define SCIDRL_RESET_MASK		(0x00)						/* 00000000 */


#define SCIPURD_PUPSCI0_BITNO	0
#define SCIPURD_PUPSCI0_MASK	(1 << SCIPURD_PUPSCI0_BITNO) /* 00000001 */
#define SCIPURD_PUPSCI1_BITNO	1
#define SCIPURD_PUPSCI1_MASK	(1 << SCIPURD_PUPSCI1_BITNO) /* 00000010 */
#define SCIPURD_RDPSCI0_BITNO	4
#define SCIPURD_RDPSCI0_MASK	(1 << SCIPURD_RDPSCI0_BITNO) /* 00010000 */
#define SCIPURD_RDPSCI1_BITNO	5
#define SCIPURD_RDPSCI1_MASK	(1 << SCIPURD_RDPSCI1_BITNO) /* 00100000 */
#define SCIPURD_SCISDOZ_BITNO	7
#define SCIPURD_SCISDOZ_MASK	(1 << SCIPURD_SCISDOZ_BITNO) /* 10000000 */

#define SCIPURD_RESET_MASK		(0x00) 						 /* 00000000 */


#define SCIPORT_PORT0_BITNO	0
#define SCIPORT_PORT0_MASK		(1 << SCIPORT_PORT0_BITNO)	/* 00000001 */
#define SCIPORT_PORT1_BITNO	1
#define SCIPORT_PORT1_MASK		(1 << SCIPORT_PORT1_BITNO)	/* 00000010 */
#define SCIPORT_PORT2_BITNO	2
#define SCIPORT_PORT2_MASK		(1 << SCIPORT_PORT2_BITNO)	/* 00000100 */
#define SCIPORT_PORT3_BITNO	3
#define SCIPORT_PORT3_MASK		(1 << SCIPORT_PORT3_BITNO)	/* 00001000 */
#define SCIPORT_PORT4_BITNO	4
#define SCIPORT_PORT4_MASK		(1 << SCIPORT_PORT4_BITNO)	/* 00010000 */
#define SCIPORT_PORT5_BITNO	5
#define SCIPORT_PORT5_MASK		(1 << SCIPORT_PORT5_BITNO)	/* 00100000 */
#define SCIPORT_PORT6_BITNO	6
#define SCIPORT_PORT6_MASK		(1 << SCIPORT_PORT6_BITNO)	/* 01000000 */
#define SCIPORT_PORT7_BITNO	7
#define SCIPORT_PORT7_MASK		(1 << SCIPORT_PORT7_BITNO)	/* 10000000 */

#define SCIPORT_PORT_MASK		(0xFF)						/* 11111111 */
#define SCIPORT_RESET_MASK		(0x00)						/* 00000000 */


#define SCIDDR_DDR0_BITNO		0
#define SCIDDR_DDR0_MASK		(1 << SCIDDR_DDR0_BITNO)	/* 00000001 */
#define SCIDDR_DDR1_BITNO		1
#define SCIDDR_DDR1_MASK		(1 << SCIDDR_DDR1_BITNO)	/* 00000010 */
#define SCIDDR_DDR2_BITNO		2
#define SCIDDR_DDR2_MASK		(1 << SCIDDR_DDR2_BITNO)	/* 00000100 */
#define SCIDDR_DDR3_BITNO		3
#define SCIDDR_DDR3_MASK		(1 << SCIDDR_DDR3_BITNO)	/* 00001000 */
#define SCIDDR_DDR4_BITNO		4
#define SCIDDR_DDR4_MASK		(1 << SCIDDR_DDR4_BITNO)	/* 00010000 */
#define SCIDDR_DDR5_BITNO		5
#define SCIDDR_DDR5_MASK		(1 << SCIDDR_DDR5_BITNO)	/* 00100000 */
#define SCIDDR_DDR6_BITNO		6
#define SCIDDR_DDR6_MASK		(1 << SCIDDR_DDR6_BITNO)	/* 01000000 */
#define SCIDDR_DDR7_BITNO		7
#define SCIDDR_DDR7_MASK		(1 << SCIDDR_DDR7_BITNO)	/* 10000000 */

#define SCIDDR_DDR_MASK			(0xFF)						/* 11111111 */
#define SCIDDR_RESET_MASK		(0x00)						/* 00000000 */


/*----------------------------------------------------------------------*/
/* Misc. Macros                                                         */
/*----------------------------------------------------------------------*/

#define MAX_7BIT_TRANSMIT_VALUE 127
#define MAX_8BIT_TRANSMIT_VALUE 255
#define MAX_9BIT_TRANSMIT_VALUE 511

#define MIN_BAUD_RATE 1
#define MIN_CLOCK_VALUE 1

#define MIN_CLOCK_DIVIDER 1
#define MAX_CLOCK_DIVIDER 8191
#define RECEIVER_ACQUISITION_RATE 16

#define SIZE_OF_REGISTER_8 8


/*----------------------------------------------------------------------*/
/* Prototypes                                                           */
/*----------------------------------------------------------------------*/

SCI_D_ReturnCode_t	SCI_D_Init_f ( pSCI_D_t, 				
								   UINT32,					
								   UINT32,				
								   SCI_D_PinMode_t,		
								   SCI_D_Idle_t,			
								   SCI_D_Parity_t,			
								   SCI_D_DataFrame_t,	
								   SCI_D_Wakeup_t,		
								   SCI_D_Control_t		
							     );


SCI_D_ReturnCode_t	SCI_D_ControlOperation_f ( pSCI_D_t,		
											   SCI_D_Control_t,	
											   SCI_D_Control_t	
											 );


SCI_D_ReturnCode_t  SCI_D_ControlInterrupt_f ( pSCI_D_t,					
											   SCI_D_Control_t,		
											   SCI_D_Control_t,	
											   SCI_D_Control_t,		
											   SCI_D_Control_t		
											 );