sci_d.h

摩托罗拉MMC2107在ucosII的移植代码

/************************************************************************/
/*	File: sci_d.h                                                       */
/*                                                                      */
/*  Purpose: File containing the structures and prototypes for the      */
/*           SCI_D device driver                                        */
/*                                                                      */
/*	(C) Copyright Motorola Inc, 2000.  All rights reserved.	            */
/*                                                                      */
/*	$RCSfile: sci_d.h,v $                                               */
/*	$Revision: 1.2 $                                                    */
/*	$Date: 2000/06/23 19:35:18 $                                        */
/*	$Author: jeffk $                                                  */
/*                                                                      */
/************************************************************************/

#ifndef _SCI_D_H
#define _SCI_D_H

#include "mcore.h"
#include "plibdefs_mmc2107.h"

/*----------------------------------------------------------------------*/
/* Enumerations                                                         */
/*----------------------------------------------------------------------*/


typedef enum
{
	SCI_D_ERR_NONE = 0x0L,				/* no error 							*/
	SCI_D_ERR_INVALID_HANDLE,			/* SCI base address parameter is zero 	*/
	SCI_D_ERR_BAD_RESULT_ADDR,			/* Result pointer is zero 				*/
	SCI_D_ERR_INVALID_ADDR,             /* Pointer is zero                      */
	SCI_D_ERR_INVALID_REGISTER,			/* Register selection is invalid 		*/
	SCI_D_ERR_INVALID_CONTROL,			/* Control selection is invalid 		*/
	SCI_D_ERR_INVALID_BAUD_RATE,		/* Baud rate is invalid 				*/
	SCI_D_ERR_INVALID_CLOCK_VALUE,		/* Clock value is invalid 				*/
	SCI_D_ERR_INVALID_CLOCK_DIVIDER, 	/* Clock divider value is invalid 		*/ 
	SCI_D_ERR_INVALID_PIN_MODE,			/* Pin mode is invalid 					*/
	SCI_D_ERR_INVALID_IDLE_MODE,		/* Idle mode is invalid 				*/
	SCI_D_ERR_INVALID_PARITY,			/* Parity selection is invalid 			*/
	SCI_D_ERR_INVALID_DATA_FRAME,		/* Data frame selection is invalid 		*/
	SCI_D_ERR_INVALID_WAKEUP_MODE,		/* Wakeup mode selection is invalid 	*/
	SCI_D_ERR_INVALID_DATA_VALUE,		/* Data frame value is invalid 			*/
	SCI_D_ERR_INVALID_RECEIVER_SOURCE,	/* Receiver source is invalid 			*/
	SCI_D_ERR_INVALID_DATA_DIRECTION,	/* Data direction is invalid 			*/
	SCI_D_ERR_INVALID_DRIVE_MODE,		/* Drive mode is invalid 				*/
	SCI_D_ERR_INVALID_PORT_NUMBER,		/* Port number selection is invalid 	*/
	SCI_D_ERR_INVALID_PIN_SENSE,		/* Pin since is invalid 				*/
	SCI_D_ERR_WAKEUP_PARITY_CONFLICT	/* Address mark wakeup and parity       */ 
                                        /* are enabled                          */
} SCI_D_ReturnCode_t;


typedef enum 
{
	SCI_D_SCIBDH,				/* Select Baud Rate Register High 		*/
	SCI_D_SCIBDL,				/* Select Baud Rate Register Low 		*/
	SCI_D_SCICR1,				/* Select Control Register 1 			*/
	SCI_D_SCICR2,				/* Select Control Register 2 			*/
	SCI_D_SCISR1,				/* Select Status Register 1 			*/
	SCI_D_SCISR2,				/* Select Status Register 2 			*/
	SCI_D_SCIDRH,				/* Select Data Register High 			*/
	SCI_D_SCIDRL,				/* Select Data Register Low 			*/
	SCI_D_SCIPURD,				/* Select Pullup and Reduced Drive Reg. */
	SCI_D_SCIPORT,				/* Select Port Data Register 			*/
	SCI_D_SCIDDR				/* Select Data Direction Register 		*/
} SCI_D_Register_t;


typedef enum 
{
	SCI_D_DISABLE,				/* Disable Selection 					*/
	SCI_D_ENABLE,				/* Enable Selection 					*/
	SCI_D_NO_CHANGE				/* Do not change selection 				*/
} SCI_D_Control_t;


typedef enum 
{
	SCI_D_FALSE,				/* false 								*/
	SCI_D_TRUE					/* true 								*/
} SCI_D_Boolean_t;

                                                                               
typedef enum {
	SCI_D_PARITY_EVEN,			/* Select even parity 					*/
	SCI_D_PARITY_ODD,			/* Select odd parity 					*/
	SCI_D_PARITY_NONE			/* Select no parity 					*/
} SCI_D_Parity_t;


typedef enum {
	SCI_D_DATA_8,				/* Select 8 bit data bits 				*/
	SCI_D_DATA_9				/* Select 9 bit data bits 				*/
} SCI_D_DataFrame_t;


typedef enum {
	SCI_D_PINMODE_CMOS,			/* CMOS output 							*/
	SCI_D_PINMODE_OPEN_DRAIN	/* Open-drain output 					*/
} SCI_D_PinMode_t;


typedef enum {
	SCI_D_IDLE_SHORT,		/* Idle character bit count begins after start bit 	*/
	SCI_D_IDLE_LONG			/* Idle character bit count begins after stop bit  	*/
} SCI_D_Idle_t;


typedef enum {
	SCI_D_WAKEUP_IDLE,		/* SCI receiver awakened by idle-line detection     */
	SCI_D_WAKEUP_ADDR		/* SCI receiver awakened by address mark            */
} SCI_D_Wakeup_t;


typedef enum {
	SCI_D_RECSOURCE_LOOP,	/* Receiver input internally connected to output    */
	SCI_D_RECSOURCE_WIRE	/* Receiver input connected to TXD pin              */
} SCI_D_RecSource_t;


typedef enum {
	SCI_D_DATADIR_INPUT,	/* Configure pin as input                           */
	SCI_D_DATADIR_OUTPUT	/* Configure pin as output                          */
} SCI_D_DataDir_t;


typedef enum {
	SCI_D_PINDRIVE_FULL,	/* Configure pin for full drive capability          */
	SCI_D_PINDRIVE_REDUCED	/* Configure pin for reduced drive capability       */
} SCI_D_PinDrive_t;


typedef enum {
	SCI_D_PORT0, 			/* Select Port 0 							*/
	SCI_D_PORT1, 			/* Select Port 1 							*/
	SCI_D_PORT2, 			/* Select Port 2 							*/
	SCI_D_PORT3,			/* Select Port 3 							*/
	SCI_D_PORT4, 			/* Select Port 4 							*/
	SCI_D_PORT5, 			/* Select Port 5 							*/
	SCI_D_PORT6, 			/* Select Port 6 							*/
	SCI_D_PORT7 			/* Select Port 7 							*/
} SCI_D_Port_t;


typedef enum {
    SCI_D_LOW,             	/* Active LOW 								*/
    SCI_D_HIGH             	/* Active HI 								*/
} SCI_D_PinSense_t;




/*----------------------------------------------------------------------*/
/*  Structures                                                          */
/*----------------------------------------------------------------------*/


typedef struct 
{
 	UINT8 SCIBDH; 					/* Baud Rate Register High 				*/
	UINT8 SCIBDL;					/* Baud Rate Register Low 				*/
	UINT8 SCICR1;					/* Control Register 1 					*/
	UINT8 SCICR2;					/* Control Register 2 					*/
	volatile UINT8 SCISR1;			/* Status Register 1 					*/
	volatile UINT8 SCISR2;			/* Status Register 2 					*/
	volatile UINT8 SCIDRH;			/* Data Register High 					*/
	volatile UINT8 SCIDRL;			/* Data Register Low 					*/
	UINT8 SCIPURD;					/* Pullup and Reduced Drive Register 	*/
	volatile UINT8 SCIPORT;			/* Port Data Register 					*/
	UINT8 SCIDDR;					/* Data Direction Register 				*/
} SCI_D_t, *pSCI_D_t;
 

typedef struct 
{
	/* Potential transmission errors */
	SCI_D_Boolean_t transmitDataPending; /* data pending error when TRUE    */

	/* Potential reception errors */	
	SCI_D_Boolean_t receiveDataPending;  /* data pending error when TRUE    */
	SCI_D_Boolean_t dataOverrun;         /* data overrun occurred when TRUE */
	SCI_D_Boolean_t noiseDetected;       /* noise detected error when TRUE  */
	SCI_D_Boolean_t framingError;        /* framing error occurred when TRUE*/
	SCI_D_Boolean_t parityError;         /* parity error occurred when TRUE */
	SCI_D_Boolean_t receiverActive;      /* receiver is busy when TRUE      */

	/* Other information */
	SCI_D_Boolean_t transmitInProgress;  /* transmit in progress when TRUE  */
	SCI_D_Boolean_t idleLine;            /* line is idle when TRUE          */

} SCI_D_Status_t, *pSCI_D_Status_t;


typedef struct 
{
	/* Potential reception errors */	
	SCI_D_Boolean_t receiveDataPending;  /* data pending error when TRUE    */
	SCI_D_Boolean_t dataOverrun;         /* data overrun occurred when TRUE */
	SCI_D_Boolean_t noiseDetected;       /* noise detected error when TRUE  */
	SCI_D_Boolean_t framingError;        /* framing error occurred when TRUE*/
	SCI_D_Boolean_t parityError;         /* parity error occurred when TRUE */
	SCI_D_Boolean_t receiverActive;      /* receiver is busy when TRUE      */

} SCI_D_ReceiverStatus_t, *pSCI_D_ReceiverStatus_t;


typedef struct 
{
	SCI_D_DataDir_t dataDirPin0;			/* port 0 data direction */
	SCI_D_DataDir_t dataDirPin1; 			/* port 1 data direction */
	SCI_D_DataDir_t dataDirPin2; 			/* port 2 data direction */
	SCI_D_DataDir_t dataDirPin3; 			/* port 3 data direction */
	SCI_D_DataDir_t dataDirPin4; 			/* port 4 data direction */
	SCI_D_DataDir_t dataDirPin5; 			/* port 5 data direction */
	SCI_D_DataDir_t dataDirPin6; 			/* port 6 data direction */
	SCI_D_DataDir_t dataDirPin7; 			/* port 7 data direction */

} SCI_D_DataDirStruct_t, *pSCI_D_DataDirStruct_t;



/*----------------------------------------------------------------------*/
/* Register Bits & Masks                                                */
/*----------------------------------------------------------------------*/

#define SCIBDH_SBR8_BITNO		0
#define SCIBDH_SBR8_MASK		(1 << SCIBDH_SBR8_BITNO)	/* 00000001 */
#define SCIBDH_SBR9_BITNO		1
#define SCIBDH_SBR9_MASK		(1 << SCIBDH_SBR9_BITNO)	/* 00000010 */
#define SCIBDH_SBR10_BITNO		2
#define SCIBDH_SBR10_MASK		(1 << SCIBDH_SBR10_BITNO)	/* 00000100 */
#define SCIBDH_SBR11_BITNO		3
#define SCIBDH_SBR11_MASK		(1 << SCIBDH_SBR11_BITNO)	/* 00001000 */
#define SCIBDH_SBR12_BITNO		4
#define SCIBDH_SBR12_MASK		(1 << SCIBDH_SBR12_BITNO)	/* 00010000 */

#define SCIBDH_SBR_BITNO		0							
#define SCIBDH_SBR_MASK			(0x1F)						/* 00011111 */
#define SCIBDH_RESET_MASK		(0x00)						/* 00000000 */