📄 qadc64_a.h
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/**********************************************************************/
/* File: qadc64_a.h File containing public API information */
/* for the QADC device driver. */
/* */
/* Design Reference: Doc. Name Version */
/* --------------------------- ------- */
/* Design Document for Level I 1.0 */
/* QADC */
/* */
/* (C) Copyright Motorola Inc, 1999. All rights reserved. */
/* */
/* $RCSfile: qadc64_a.h,v $ */
/* $Revision: 1.1 $ */
/* $Date: 2000/06/23 20:22:21 $ */
/* $Author: jeffk $ */
/* */
/**********************************************************************/
#include "mcore.h"
#ifndef _QADC64_A_H
#define _QADC64_A_H
/* These macros can be used with the QADCMCR */
#define QADCMCR_STOP_BITNO 15
#define QADCMCR_STOP_MASK (1 << QADCMCR_STOP_BITNO)
#define QADCMCR_FRZ_BITNO 14
#define QADCMCR_FRZ_MASK (1 << QADCMCR_FRZ_BITNO)
#define QADCMCR_SUPV_BITNO 7
#define QADCMCR_SUPV_MASK (1 << QADCMCR_SUPV_BITNO)
#define QADCMCR_IARB_BITNO 0
#define MINIMUM_IARB_VALUE 1
#define MAXIMUM_IARB_VALUE 0x0f
#define QADCMCR_IARB_MASK (MAXIMUM_IARB_VALUE << QADCMCR_IARB_BITNO)
/* These macros can be used with the PORTQA/PORTQB */
#define PORTQA_PQA7_BITNO 15
#define PORTQA_PQA7_MASK (1 << PORTQA_PQA7_BITNO)
#define PORTQA_PQA6_BITNO 14
#define PORTQA_PQA6_MASK (1 << PORTQA_PQA6_BITNO)
#define PORTQA_PQA5_BITNO 13
#define PORTQA_PQA5_MASK (1 << PORTQA_PQA5_BITNO)
#define PORTQA_PQA4_BITNO 12
#define PORTQA_PQA4_MASK (1 << PORTQA_PQA4_BITNO)
#define PORTQA_PQA3_BITNO 11
#define PORTQA_PQA3_MASK (1 << PORTQA_PQA3_BITNO)
#define PORTQA_PQA2_BITNO 10
#define PORTQA_PQA2_MASK (1 << PORTQA_PQA2_BITNO)
#define PORTQA_PQA1_BITNO 9
#define PORTQA_PQA1_MASK (1 << PORTQA_PQA1_BITNO)
#define PORTQA_PQA0_BITNO 8
#define PORTQA_PQA0_MASK (1 << PORTQA_PQA0_BITNO)
#define PORTQB_PQB7_BITNO 7
#define PORTQB_PQB7_MASK (1 << PORTQB_PQB7_BITNO)
#define PORTQB_PQB6_BITNO 6
#define PORTQB_PQB6_MASK (1 << PORTQB_PQB6_BITNO)
#define PORTQB_PQB5_BITNO 5
#define PORTQB_PQB5_MASK (1 << PORTQB_PQB5_BITNO)
#define PORTQB_PQB4_BITNO 4
#define PORTQB_PQB4_MASK (1 << PORTQB_PQB4_BITNO)
#define PORTQB_PQB3_BITNO 3
#define PORTQB_PQB3_MASK (1 << PORTQB_PQB3_BITNO)
#define PORTQB_PQB2_BITNO 2
#define PORTQB_PQB2_MASK (1 << PORTQB_PQB2_BITNO)
#define PORTQB_PQB1_BITNO 1
#define PORTQB_PQB1_MASK (1 << PORTQB_PQB1_BITNO)
#define PORTQB_PQB0_BITNO 0
#define PORTQB_PQB0_MASK (1 << PORTQB_PQB0_BITNO)
/* These macros can be used with the DDRQA */
#define DDRQA_DDQA7_BITNO 15
#define DDRQA_DDQA7_MASK (1 << DDRQA_DDQA7_BITNO)
#define DDRQA_DDQA6_BITNO 14
#define DDRQA_DDQA6_MASK (1 << DDRQA_DDQA6_BITNO)
#define DDRQA_DDQA5_BITNO 13
#define DDRQA_DDQA5_MASK (1 << DDRQA_DDQA5_BITNO)
#define DDRQA_DDQA4_BITNO 12
#define DDRQA_DDQA4_MASK (1 << DDRQA_DDQA4_BITNO)
#define DDRQA_DDQA3_BITNO 11
#define DDRQA_DDQA3_MASK (1 << DDRQA_DDQA3_BITNO)
#define DDRQA_DDQA2_BITNO 10
#define DDRQA_DDQA2_MASK (1 << DDRQA_DDQA2_BITNO)
#define DDRQA_DDQA1_BITNO 9
#define DDRQA_DDQA1_MASK (1 << DDRQA_DDQA1_BITNO)
#define DDRQA_DDQA0_BITNO 8
#define DDRQA_DDQA0_MASK (1 << DDRQA_DDQA0_BITNO)
/* These macros can be used with the QACR0 */
#define QACR0_MUX_BITNO 15
#define QACR0_MUX_MASK (1 << QACR0_MUX_BITNO)
#define QACR0_TRG_BITNO 12
#define QACR0_TRG_MASK (1 << QACR0_TRG_BITNO)
#define QACR0_PSH_BITNO 4
#define MAXIMUM_PRESCALER_HIGH_TIME 0x1f
#define QACR0_PSH_MASK (MAXIMUM_PRESCALER_HIGH_TIME << QACR0_PSH_BITNO)
#define QACR0_PSA_BITNO 3
#define QACR0_PSA_MASK (1 << QACR0_PSA_BITNO)
#define QACR0_PSL_BITNO 0
#define MAXIMUM_PRESCALER_LOW_TIME 0x07
#define QACR0_PSL_MASK (MAXIMUM_PRESCALER_LOW_TIME << QACR0_PSL_BITNO)
/* These macros can be used with the QACR1 or QACR2 */
#define QACRx_CIEx_BITNO 15
#define QACRx_CIEx_MASK (1 << QACRx_CIEx_BITNO)
#define QACRx_PIEx_BITNO 14
#define QACRx_PIEx_MASK (1 << QACRx_PIEx_BITNO)
#define QACRx_SSEx_BITNO 13
#define QACRx_SSEx_MASK (1 << QACRx_SSEx_BITNO)
#define QACRx_MQx_BITNO 8
#define MAXIMUM_OPERATING_MODE 31
#define QACRx_MQx_MASK (MAXIMUM_OPERATING_MODE << QACRx_MQx_BITNO)
/* These macros can be used with QACR2 */
#define QACR2_RESUME_BITNO 7
#define QACR2_RESUME_MASK (1 << QACR2_RESUME_BITNO)
#define QACR2_BQ2_BITNO 0
#define MAXIMUM_BQ2 0x7f
#define QACR2_BQ2_MASK (MAXIMUM_BQ2 << QACR2_BQ2_BITNO)
/* These macros can be used with the QASR0 */
#define QASR0_CF1_BITNO 15
#define QASR0_CF1_MASK (1 << QASR0_CF1_BITNO)
#define QASR0_PF1_BITNO 14
#define QASR0_PF1_MASK (1 << QASR0_PF1_BITNO)
#define QASR0_CF2_BITNO 13
#define QASR0_CF2_MASK (1 << QASR0_CF2_BITNO)
#define QASR0_PF2_BITNO 12
#define QASR0_PF2_MASK (1 << QASR0_PF2_BITNO)
#define QASR0_TOR1_BITNO 11
#define QASR0_TOR1_MASK (1 << QASR0_TOR1_BITNO)
#define QASR0_TOR2_BITNO 10
#define QASR0_TOR2_MASK (1 << QASR0_TOR2_BITNO)
#define QASR0_QS_BITNO 6
#define QASR0_QS_MASK (0x0f << QASR0_QS_BITNO)
#define QASR0_CWP_BITNO 0
#define QASR0_CWP_MASK (0x3f << QASR0_CWP_BITNO)
/* These macros can be used with QASR1 */
#define QASR1_CWPQ1_BITNO 8
#define QASR1_CWPQ1_MASK (0x3f << QASR1_CWPQ1_BITNO)
#define QASR1_CWPQ2_BITNO 0
#define QASR1_CWPQ2_MASK (0x3f << QASR1_CWPQ2_BITNO)
/* These macros can be used with any CCW */
#define CCW_PAUSE_BITNO 9
#define CCW_PAUSE_MASK (1 << CCW_PAUSE_BITNO)
#define CCW_BYP_BITNO 8
#define CCW_BYP_MASK (1 << CCW_BYP_BITNO)
#define CCW_IST_BITNO 6
#define MAXIMUM_IST 3
#define CCW_IST_MASK (MAXIMUM_IST << CCW_IST_BITNO)
#define CCW_CHAN_BITNO 0
#define MAXIMUM_CHANNEL 63
#define CCW_CHAN_MASK (MAXIMUM_CHANNEL << CCW_CHAN_BITNO)
#define MINIMUM_RESERVED_CHANNEL 32
#define MAXIMUM_RESERVED_CHANNEL 47
#define MAXIMUM_CCW 63
/* These macros can be used with QADCINT */
#define QADCINT_IRL1_BITNO 11
#define MAXIMUM_IRL 0x1f
#define QADCINT_IRL1_MASK (MAXIMUM_IRL << QADCINT_IRL1_BITNO)
#define QADCINT_IRL2_BITNO 6
#define QADCINT_IRL2_MASK (0x1f << QADCINT_IRL2_BITNO)
/*--------------------------------------------------------------------*/
/* Enumerations */
/*--------------------------------------------------------------------*/
/***** QADC64_A_ReturnCode_t - QADC64_A Error Codes ********************/
typedef enum
{
QADC64_A_ERR_NONE = 0x0L, /* no error */
QADC64_A_ERR_INVALID_HANDLE, /* PLL base address is zero */
QADC64_A_ERR_BAD_RESULT_ADDR, /* Result pointer is zero */
QADC64_A_ERR_INVALID_REGISTER, /* Register selection if invalid */
QADC64_A_ERR_INVALID_DATA_FORMAT, /* Data Format is invalid */
QADC64_A_ERR_INVALID_IARB, /* Aribitratoin Flag - N/A */
QADC64_A_ERR_INVALID_QCLK_PSH, /* High Time QCLK Prescaler Clck */
QADC64_A_ERR_INVALID_QCLK_PSL, /* Low Time QCLK Prescaler Clock */
QADC64_A_ERR_INVALID_TRIGGER_ASSIGNMENT,/*Invalid Trigger Assgnment*/
QADC64_A_ERR_INVALID_IRL, /* Invalid Interrupt Request */
QADC64_A_ERR_INVALID_BQ2, /* Invalid Beginning of Queue 2 */
QADC64_A_ERR_INVALID_CCW, /* Invalid Conversion Command */
QADC64_A_ERR_INVALID_IST, /* Invalid Input Sample Time */
QADC64_A_ERR_INVALID_CHANNEL, /* Invalid Channel Number */
QADC64_A_ERR_INVALID_MODE, /* Specified Queue Operating */
QADC64_A_ERR_INVALID_RESET, /* Specified Status Reset Flags */
QADC64_A_ERR_INVALID_RESULT_WORD /* Table entry is invalid */
} QADC64_A_ReturnCode_t;
typedef enum
{
QADC64_A_FALSE, /* PLL false flag indicator */
QADC64_A_TRUE /* PLL true flag indicator */
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