📄 cs_a.h
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/************************************************************************/
/* File: cs_a.h */
/* */
/* Purpose: File containing the structures and prototypes for the */
/* CS_A device driver */
/* */
/* (C) Copyright Metrowerks, 2000. All rights reserved. */
/* */
/* $RCSfile: cs_a.h,v $ */
/* $Revision: 1.1 $ */
/* $Date: 2000/06/23 20:22:20 $ */
/* $Author: jeffk $ */
/* */
/************************************************************************/
#ifndef _CS_A_H
#define _CS_A_H
#include "mcore.h"
#include "plibdefs_mmc2107.h"
/*----------------------------------------------------------------------*/
/* Enumerations */
/*----------------------------------------------------------------------*/
typedef enum{
CS_A_ERR_NONE,
CS_A_ERR_INVALID_HANDLE,
CS_A_ERR_BAD_RESULT_ADDR,
CS_A_ERR_INVALID_REGISTER,
CS_A_ERR_INVALID_CONTROL,
CS_A_ERR_INVALID_TRANSFER_ACK_VAL,
CS_A_ERR_INVALID_WRITE_ENABLE_VAL,
CS_A_ERR_INVALID_WAIT_STATE_VAL,
CS_A_ERR_INVALID_WRITE_WAIT_STATE_VAL,
CS_A_ERR_INVALID_PORT_SIZE_VAL,
CS_A_ERR_INVALID_READ_ONLY_VAL,
CS_A_ERR_INVALID_SUPERVISOR_ONLY_VAL,
CS_A_ERR_INVALID_CHIP_SELECT_ENABLE_VAL,
CS_A_ERR_INVALID_RESET_CONDITION_VAL
} CS_A_ReturnCode_t; /* CS_A return codes */
typedef enum {
CS_A_CSCR0, /* Select chip select register 0 */
CS_A_CSCR1, /* Select chip select register 1 */
CS_A_CSCR2, /* Select chip select register 2 */
CS_A_CSCR3 /* Select chip select register 3 */
} CS_A_RegisterSwitch_t;
typedef enum {
CS_A_DISABLE, /* Select DISABLE */
CS_A_ENABLE /* Select ENABLE */
} CS_A_Control_t;
typedef enum{
CS_A_FALSE, /* Logical value FALSE */
CS_A_TRUE /* Logical value TRUE */
} CS_A_Boolean_t; /* CS_A boolean enum */
typedef enum {
CS_A_CHIP_SELECT_DISABLE, /* Enable Chip Select */
CS_A_CHIP_SELECT_ENABLE /* Disable Chip Select */
} CS_A_ChipSelectControl_t;
typedef enum {
CS_A_EXTERNAL_LOGIC_ASSERTION, /* external logic */
CS_A_CHIP_SELECT_LOGIC_ASSERTION /* chip select */
} CS_A_TransferAckControl_t;
/* Wait State Selection */
typedef enum {
CS_A_WAIT_STATE_ZERO,
CS_A_WAIT_STATE_ONE,
CS_A_WAIT_STATE_TWO,
CS_A_WAIT_STATE_THREE,
CS_A_WAIT_STATE_FOUR,
CS_A_WAIT_STATE_FIVE,
CS_A_WAIT_STATE_SIX
} CS_A_WaitStates_t;
typedef enum {
CS_A_WRITE_AS_BYTES_ENABLE, /* Enable Write as Bytes */
CS_A_EXTERNAL_WRITE_ENABLE /* Enable Write Enable */
} CS_A_WriteEnable_t;
/* Write Cycle Wait State Selection */
typedef enum {
CS_A_NO_WAIT_STATE_ADD, /* No wait state is added to write cycle */
CS_A_ADD_ONE_WAIT_STATE /* One wait state added for write cycle */
} CS_A_WriteWaitState_t;
/* Port Size Selection */
typedef enum {
CS_A_PORT_SIZE_16, /* Port Size 16 */
CS_A_PORT_SIZE_32 /* Port Size 32 */
} CS_A_PortSize_t;
/* Read Only Selection */
typedef enum {
CS_A_READ_WRITE_ENABLE, /* Read and write accesses are allowed */
CS_A_READ_ONLY_ENABLE /* Read Only accesses allowed */
} CS_A_ReadOnly_t;
/* Reset Condition Selection */
typedef enum {
CS_A_EMULATION_MODE, /* Read and write accesses are allowed */
CS_A_16_BIT_PORT_SIZE_ENABLE, /* Read Only accesses allowed */
CS_A_32_BIT_PORT_SIZE_ENABLE /* Read Only accesses allowed */
} CS_A_ResetCondition_t;
/* Supervisor Only Selection */
typedef enum {
CS_A_SUPERVISOR_AND_USER_ENABLE, /* Supervisor and user allowed */
CS_A_SUPERVISOR_ONLY_ENABLE /* Supervisor Only allowed */
} CS_A_SupervisorOnly_t;
/*----------------------------------------------------------------------*/
/* Structures */
/*----------------------------------------------------------------------*/
typedef struct
{
UINT16 CSCR0; /* Chip Select Register 0 */
UINT16 CSCR1; /* Chip Select Register 1 */
UINT16 CSCR2; /* Chip Select Register 2 */
UINT16 CSCR3; /* Chip Select Register 3 */
} CS_A_t, *pCS_A_t;
/*----------------------------------------------------------------------*/
/* Register Bits & Masks */
/*----------------------------------------------------------------------*/
/* Control Register */
#define CSCRX_SO_BITNO 15
#define CSCRX_SO_MASK (1 << CSCRX_SO_BITNO)
#define CSCRX_RO_BITNO 14
#define CSCRX_RO_MASK (1 << CSCRX_RO_BITNO)
#define CSCRX_PS_BITNO 13
#define CSCRX_PS_MASK (1 << CSCRX_PS_BITNO)
#define CSCRX_WWS_BITNO 12
#define CSCRX_WWS_MASK (1 << CSCRX_WWS_BITNO)
#define CSCRX_WE_BITNO 11
#define CSCRX_WE_MASK (1 << CSCRX_WE_BITNO)
#define CSCRX_WS_MAX 0x7
#define CSCRX_WS_BITNO 8
#define CSCRX_WS_MASK (CSCRX_WS_MAX << CSCRX_WS_BITNO)
#define CSCRX_TAEN_BITNO 1
#define CSCRX_TAEN_MASK (1 << CSCRX_TAEN_BITNO)
#define CSCRX_CSEN_BITNO 0
#define CSCRX_CSEN_MASK (1 << CSCRX_CSEN_BITNO)
/* Control Register 0 */
#define CSCR0_RESET_MASK_16_BIT_PORT_CONDITION 0x1F03
#define CSCR0_RESET_MASK_32_BIT_PORT_CONDITION 0x3F03
#define CSCR0_RESET_MASK_EMULATION_CONDITION 0x3F02
/* Control Register 1 */
#define CSCR1_RESET_MASK_16_BIT_PORT_CONDITION 0x1F02
#define CSCR1_RESET_MASK_32_BIT_PORT_CONDITION 0x3F02
#define CSCR1_RESET_MASK_EMULATION_CONDITION 0x3F03
/* Control Register 2 */
#define CSCR2_RESET_MASK 0x3F02
/* Control Register 3 */
#define CSCR3_RESET_MASK 0x3F02
/*----------------------------------------------------------------------*/
/* Prototypes */
/*----------------------------------------------------------------------*/
CS_A_ReturnCode_t CS_A_Reset_f ( pCS_A_t,
CS_A_ResetCondition_t
);
CS_A_ReturnCode_t CS_A_ConfigureChipSelectFeatures_f ( pCS_A_t,
CS_A_RegisterSwitch_t,
CS_A_TransferAckControl_t,
CS_A_WaitStates_t,
CS_A_WriteEnable_t,
CS_A_WriteWaitState_t,
CS_A_PortSize_t,
CS_A_ReadOnly_t,
CS_A_SupervisorOnly_t
);
CS_A_ReturnCode_t CS_A_ControlChipSelect_f ( pCS_A_t,
CS_A_RegisterSwitch_t,
CS_A_ChipSelectControl_t
);
CS_A_ReturnCode_t CS_A_SetRegister_f (
pCS_A_t,
CS_A_RegisterSwitch_t,
UINT16
);
CS_A_ReturnCode_t CS_A_GetRegister_f (
pCS_A_t,
CS_A_RegisterSwitch_t,
UINT16 *
);
/*----------------------------------------------------------------------*/
/* Macro: CS_A_ControlChipSelect */
/* */
/* Purpose: CS_A_ControlChipSelect enables or disables the chip */
/* select features. Parameter checking is a compile time */
/* option. */
/* */
/* Input: */
/* CSPtr : CS module base address associated with */
/* this driver. */
/* CSRegSwitch : Select among CS_A registers. */
/* ChipSelectEnableVal : Enable or disable the chip select module. */
/* */
/* Output: */
/* CS_A_ERR_NONE : No error. */
/* CS_A_ERR_INVALID_HANDLE : CS module base address parameter is */
/* zero. */
/* CS_A_ERR_INVALID_CHIP_SELECT_ENABLE_VAL : Invalid chip select enable*/
/* value. */
/* CS_A_ERR_INVALID_REGISTER : CS Register Selection switch is invalid.*/
/*----------------------------------------------------------------------*/
#define CS_A_ControlChipSelect(CSPtr, \
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