📄 itcn_b.h
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#define FIPR_FIP23_MASK (1 << FIPR_FIP23_BITNO)
#define FIPR_FIP22_BITNO 22
#define FIPR_FIP22_MASK (1 << FIPR_FIP22_BITNO)
#define FIPR_FIP21_BITNO 21
#define FIPR_FIP21_MASK (1 << FIPR_FIP21_BITNO)
#define FIPR_FIP20_BITNO 20
#define FIPR_FIP20_MASK (1 << FIPR_FIP20_BITNO)
#define FIPR_FIP19_BITNO 19
#define FIPR_FIP19_MASK (1 << FIPR_FIP19_BITNO)
#define FIPR_FIP18_BITNO 18
#define FIPR_FIP18_MASK (1 << FIPR_FIP18_BITNO)
#define FIPR_FIP17_BITNO 17
#define FIPR_FIP17_MASK (1 << FIPR_FIP17_BITNO)
#define FIPR_FIP16_BITNO 16
#define FIPR_FIP16_MASK (1 << FIPR_FIP16_BITNO)
#define FIPR_FIP15_BITNO 15
#define FIPR_FIP15_MASK (1 << FIPR_FIP15_BITNO)
#define FIPR_FIP14_BITNO 14
#define FIPR_FIP14_MASK (1 << FIPR_FIP14_BITNO)
#define FIPR_FIP13_BITNO 13
#define FIPR_FIP13_MASK (1 << FIPR_FIP13_BITNO)
#define FIPR_FIP12_BITNO 12
#define FIPR_FIP12_MASK (1 << FIPR_FIP12_BITNO)
#define FIPR_FIP11_BITNO 11
#define FIPR_FIP11_MASK (1 << FIPR_FIP11_BITNO)
#define FIPR_FIP10_BITNO 10
#define FIPR_FIP10_MASK (1 << FIPR_FIP10_BITNO)
#define FIPR_FIP9_BITNO 9
#define FIPR_FIP9_MASK (1 << FIPR_FIP9_BITNO)
#define FIPR_FIP8_BITNO 8
#define FIPR_FIP8_MASK (1 << FIPR_FIP8_BITNO)
#define FIPR_FIP7_BITNO 7
#define FIPR_FIP7_MASK (1 << FIPR_FIP7_BITNO)
#define FIPR_FIP6_BITNO 6
#define FIPR_FIP6_MASK (1 << FIPR_FIP6_BITNO)
#define FIPR_FIP5_BITNO 5
#define FIPR_FIP5_MASK (1 << FIPR_FIP5_BITNO)
#define FIPR_FIP4_BITNO 4
#define FIPR_FIP4_MASK (1 << FIPR_FIP4_BITNO)
#define FIPR_FIP3_BITNO 3
#define FIPR_FIP3_MASK (1 << FIPR_FIP3_BITNO)
#define FIPR_FIP2_BITNO 2
#define FIPR_FIP2_MASK (1 << FIPR_FIP2_BITNO)
#define FIPR_FIP1_BITNO 1
#define FIPR_FIP1_MASK (1 << FIPR_FIP1_BITNO)
#define FIPR_FIP0_BITNO 0
#define FIPR_FIP0_MASK (1 << FIPR_FIP0_BITNO)
#define FIPR_FIP_MASK (0xFFFFFFFF)
#define FIPR_RESET_MASK (0x00000000)
/*- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
/* PLSR Bits & Masks */
/*- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - */
#define PLSR_PLS_BITNO 0
#define PLSR_PLS_MAX 0x1F
#define PLSR_PLS_MASK (PLSR0_PLS_MAX << PLSR0_PLS_BITNO)
#define PLSR_RESET_MASK (0x00)
/*----------------------------------------------------------------------*/
/* Misc. Macros */
/*----------------------------------------------------------------------*/
/* vector table positions */
#define AUTOVECTOR_NORMAL_INTERRUPTS 10
#define AUTOVECTOR_FAST_INTERRUPTS 11
#define VECTOR_NORMAL_INTERRUPTS_BEGIN 32
#define VECTOR_NORMAL_INTERRUPTS_END 63
#define VECTOR_FAST_INTERRUPTS_BEGIN 64
#define VECTOR_FAST_INTERRUPTS_END 95
/* priority level macros */
#define INTERRUPT_PRIORITY_LEVEL_MIN 0
#define INTERRUPT_PRIORITY_LEVEL_MAX 31
/* register misc. macros */
#define REGISTER_8BIT_MAX 0xFF
#define REGISTER_16BIT_MAX 0xFFFF
#define REGISTER_32BIT_MAX 0xFFFFFFFF
#define REGISTER_8BIT_MIN 0
#define REGISTER_16BIT_MIN 0
#define REGISTER_32BIT_MIN 0
#define REGISTER_8BIT_BITS 8
#define REGISTER_16BIT_BITS 16
#define REGISTER_32BIT_BITS 32
/*----------------------------------------------------------------------*/
/* Prototypes */
/*----------------------------------------------------------------------*/
ITCN_B_ReturnCode_t ITCN_B_Init_f ( pITCN_B_t,
ITCN_B_Autovector_t,
ITCN_B_FastInterruptControl_t,
ITCN_B_Mask_t,
UINT8 );
ITCN_B_ReturnCode_t ITCN_B_InitVectorTable_f ( pITCN_B_t,
UINT32,
UINT32 );
ITCN_B_ReturnCode_t ITCN_B_SetInterruptServiceRoutine_f (
pITCN_B_t,
UINT8,
ITCN_B_InterruptType_t,
UINT32,
ITCN_B_InterruptSource_t,
ITCN_B_Autovector_t );
ITCN_B_ReturnCode_t ITCN_B_ControlOperation_f (
pITCN_B_t,
UINT8,
ITCN_B_InterruptType_t,
ITCN_B_InterruptControl_t );
ITCN_B_ReturnCode_t ITCN_B_ForceInterrupt_f ( pITCN_B_t,
ITCN_B_InterruptSource_t,
ITCN_B_Force_t );
ITCN_B_ReturnCode_t ITCN_B_GetStatus_f ( pITCN_B_t,
pITCN_B_Status_t );
ITCN_B_ReturnCode_t ITCN_B_SetRegister_f ( pITCN_B_t,
ITCN_B_Register_t,
UINT32 );
ITCN_B_ReturnCode_t ITCN_B_GetRegister_f ( pITCN_B_t,
ITCN_B_Register_t,
UINT32 * );
ITCN_B_ReturnCode_t ITCN_B_Reset_f ( pITCN_B_t );
/************************************************************************/
/* Macro: ITCN_B_Init */
/* */
/* Purpose: Call ITCN_B_Init_f function with optional */
/* parameter checking. */
/* */
/* Input: */
/* ITCNPtr : ITCN base address associated with */
/* this driver. */
/* vectorType : specify vectored or autovectored interrupts */
/* fastInterruptControl : enable or disable fast interrupts */
/* maskMode : specify mask mode */
/* maskLevel : specify mask level */
/* Output: */
/* ITCN_B_ERR_NONE : No error. */
/* ITCN_B_ERR_INVALID_HANDLE : ITCN base address parameter is zero. */
/* ITCN_B_ERR_INVALID_VECTOR_TYPE : Invalid vector type */
/* ITCN_B_ERR_INVALID_FAST_INTERRUPT_CONTROL : Invalid fast interrupt */
/* control selection */
/* ITCN_B_ERR_INVALID_MASK_MODE : Invalid mask mode */
/* ITCN_B_ERR_INVALID_MASK_LEVEL : Invalid mask level */
/************************************************************************/
#define ITCN_B_Init( ITCNPtr, \
vectorType, \
fastInterruptControl, \
maskMode, \
maskLevel ) \
( \
(ITCN_B_PARAM_CHECKING) ? \
( \
((ITCNPtr) == NULL) ? \
ITCN_B_ERR_INVALID_HANDLE : \
(((vectorType) < ITCN_B_VECTORED_INTERRUPTS) || \
((vectorType) > ITCN_B_AUTOVECTORED_INTERRUPTS)) ? \
ITCN_B_ERR_INVALID_VECTOR_TYPE : \
(((fastInterruptControl) < ITCN_B_FAST_INTERRUPT_DISABLE) || \
((fastInterruptControl) > ITCN_B_FAST_INTERRUPT_ENABLE)) ? \
ITCN_B_ERR_INVALID_FAST_INTERRUPT_CONTROL : \
(((maskMode) < ITCN_B_MASK_DISABLE) || \
((maskMode) > ITCN_B_MASK_ENABLE_FAST_AND_NORMAL)) ? \
ITCN_B_ERR_INVALID_MASK_MODE : \
(((maskLevel) < INTERRUPT_PRIORITY_LEVEL_MIN) || \
((maskLevel) > INTERRUPT_PRIORITY_LEVEL_MAX)) ? \
ITCN_B_ERR_INVALID_MASK_LEVEL : \
ITCN_B_Init_f( (ITCNPtr), \
(vectorType), \
(fastInterruptControl), \
(maskMode), \
(maskLevel) ) \
) \
: \
ITCN_B_Init_f( (ITCNPtr), \
(vectorType), \
(fastInterruptControl), \
(maskMode), \
(maskLevel) ) \
) /* end of ITCN_B_Init Macro */
/************************************************************************/
/* Macro: ITCN_B_InitVectorTable */
/* */
/* Purpose: Call ITCN_B_InitVectorTable_f with optional parameter */
/* checking. */
/* */
/* Input: */
/* ITCNPtr : ITCN base address associated with this driver. */
/* NormISR : Pointer to user-specified default normal ISR. */
/* FastISR : Pointer to user-specified default fast ISR. */
/* */
/* Output: */
/* ITCN_B_ERR_NONE : No error */
/* ITCN_B_ERR_INVALID_HANDLE : ITCN base address parameter is zero */
/************************************************************************/
#define ITCN_B_InitVectorTable( ITCNPtr, \
normISR, \
fastISR ) \
( \
(ITCN_B_PARAM_CHECKING) ? \
( \
((ITCNPtr) == NULL) ? \
ITCN_B_ERR_INVALID_HANDLE : \
ITCN_B_InitVectorTable_f( (ITCNPtr), \
(normISR), \
(fastISR) ) \
) \
: \
ITCN_B_InitVectorTable_f( (ITCNPtr), \
(normISR), \
(fastISR) ) \
) /* End of ITCN_B_InitVectorTable Macro */
/************************************************************************/
/* Macro: ITCN_B_SetInterruptServiceRoutine */
/* */
/* Purpose: Call ITCN_B_SetInterruptServiceRoutine_f with optional */
/* parameter checking. */
/* */
/* Input: */
/* ITCNPtr : ITCN base address associated with this driver. */
/* priorityLevel : priority level for this interrupt */
/* interruptType : specify fast or normal interrupt */
/* ISRAddress : pointer to an ISR */
/* interruptSource : source of interrupt */
/* vectorType : specify vectored or autovectored interrupt */
/* */
/* Output: */
/* ITCN_B_ERR_NONE : No error */
/* ITCN_B_ERR_INVALID_HANDLE : ITCN base address parameter is zero */
/* ITCN_B_ERR_INVALID_PRIORITY_LEVEL : priority level is invalid */
/* ITCN_B_ERR_INVALID_INTERRUPT_TYPE : invalid interrupt type */
/* ITCN_B_ERR_INVALID_ISR_ADDRESS : ISR address is zero */
/* ITCN_B_ERR_INVALID_INTERRUPT_SOURCE : invalid interrupt source */
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