imx21-registers.h

ucosII在DRAGONBALL MX21上的移植 开发环境为IAR

                                                                         /* CSPI1, not used                                      */
#define  RxData1                             (*((INT32U *)0x1000E000))   /* Receive Data Register 1                              */
#define  TxData1                             (*((INT32U *)0x1000E004))   /* Transmit Data Register 1                             */
#define  ControlReg1                         (*((INT32U *)0x1000E008))   /* Control Register 1                                   */
#define  INT1                                (*((INT32U *)0x1000E00C))   /* Interrupt Control/Status Register 1                  */
#define  Test1                               (*((INT32U *)0x1000E010))   /* Test Register 1                                      */
#define  Period1                             (*((INT32U *)0x1000E014))   /* Period Control Register 1                            */
#define  DMA1                                (*((INT32U *)0x1000E018))   /* DMA1 (not used)                                      */
#define  Reset1                              (*((INT32U *)0x1000E01C))   /* Soft Reset Register 1                                */

                                                                         /* SDHC, MMC Host Controller -- 1 --                    */
#define  STR_STP_CLK                         (*((INT32U *)0x10013000))   /* MMC/SD Clock Control Register                        */
#define  STATUS                              (*((INT32U *)0x10013004))   /* MMC/SD Status Register                               */
#define  CLK_RATE                            (*((INT32U *)0x10013008))   /* MMC/SD Clock Rate Register                           */
#define  CMD_DAT_CONT                        (*((INT32U *)0x1001300C))   /* MMC/SD Command and Data Control Register             */
#define  RES_TO                              (*((INT32U *)0x10013010))   /* MMC/SD Response Time Out Register                    */
#define  READ_TO                             (*((INT32U *)0x10013014))   /* MMC/SD Read Time Out Register                        */
#define  BLK_LEN                             (*((INT32U *)0x10013018))   /* MMC/SD Block Length Register                         */
#define  NOB                                 (*((INT32U *)0x1001301C))   /* MMC/SD Number of Block Register                      */
#define  REV_NO                              (*((INT32U *)0x10013020))   /* MMC/SD Revision Number Register                      */
#define  INT_CNTR                            (*((INT32U *)0x10013024))   /* MMC/SD Interrupt Control Register                    */
#define  CMD                                 (*((INT32U *)0x10013028))   /* MMC/SD Command Number Register                       */
#define  ARGH                                (*((INT32U *)0x1001302C))   /* MMC/SD Higher Argument Register                      */
#define  ARGL                                (*((INT32U *)0x10013030))   /* MMC/SD Lower Argument Register                       */
#define  RES_FIFO                            (*((INT32U *)0x10013034))   /* MMC/SD Response FIFO Register                        */
#define  BUFFER_ACCESS                       (*((INT32U *)0x10013038))   /* MMC/SD Buffer Access Register                        */

                                                                         /* CSPI3 - attached to MMC/SD HC                        */
#define  RxData3                             (*((INT32U *)0x10017000))   /* Receive Data Register 3                              */
#define  TxData3                             (*((INT32U *)0x10017004))   /* Transmit Data Register 3                             */
#define  ControlReg3                         (*((INT32U *)0x10017008))   /* Control Register 3                                   */
#define  INT3                                (*((INT32U *)0x1001700C))   /* Interrupt Control/Status Register 3                  */
#define  Test3                               (*((INT32U *)0x10017010))   /* Test Register 3                                      */
#define  Period3                             (*((INT32U *)0x10017014))   /* RPeriod Control Register 3                           */
#define  DMA3                                (*((INT32U *)0x10017018))   /* DMA Register 3                                       */
#define  Reset3                              (*((INT32U *)0x1001701C))   /* Soft Reset Register 3                                */

/*
*********************************************************************************************************
*                                              Register Bit Definitions
*********************************************************************************************************
*/
                                                                         /* PLL and system clocks                                */
#define  MPLL_RESTART               (1 << 21)                            /* CSCR MPLL Restart bit. Write 1 to set, self clears   */
#define  SPLL_RESTART               (1 << 22)                            /* CSCR SPLL Restart bit. Write 1 to set, self clears   */
#define  MPLL_LF                    (1 << 15)                            /* MPCTL1 MPLL lock flag status, 1 = locked             */
#define  SPLL_LF                    (1 << 15)                            /* SPCTL1 SPLL lock flag status, 1 = locked             */

                                                                         /* UART                                                 */
#define  UART_RRDYEN                (1 <<  9)                            /* UCR1 receive data interrupt enable                   */
#define  UART_RRDY                  (1 <<  9)                            /* USR1 data received bit                               */
#define  UART_TRDYEN                (1 << 13)                            /* UCR1 transmit interrupt complete enable              */
#define  UART_TRDY                  (1 << 13)                            /* USR1 data transmitted bit                            */
#define  UART_DREN                  (1 <<  0)                            /* UCR4 receive data ready interrupt enable             */
#define  UART_TCEN                  (1 <<  3)                            /* UCR4 transmit complete interrupt enable              */
#define  UART_TRDY                  (1 << 13)                            /* USR1 data transmitted bit                            */
#define  UART_TRDY                  (1 << 13)                            /* USR1 data transmitted bit                            */
#define  UART_IRTS                  (1 << 14)                            /* UCR2 ignore rts pin when bit 14 is set               */
#define  UART_PARTITY_ERR           (1 << 15)                            /* USR1 Partity Error Int. flag. Write 1 to clear       */
#define  UART_RTSD                  (1 << 13)                            /* USR1 RTS delta Int. flag. Write 1 to clear           */
#define  UART_ESCF                  (1 << 11)                            /* USR1 Escape sequence Int. flag. Write 1 to clear     */
#define  UART_FRAMERR               (1 << 10)                            /* USR1 Frame error Int. flag. Write 1 to clear         */
#define  UART_AGTIM                 (1 <<  8)                            /* USR1 Aging timer Int. flag. Write 1 to clear         */
#define  UART_AIRINT                (1 <<  5)                            /* USR1 Async IR wake Int.flag. Write 1 to clear        */
#define  UART_AWAKE                 (1 <<  4)                            /* USR1 Async wake Int. flag. Write 1 to clear          */
#define  UART_ADET                  (1 << 15)                            /* USR2 Auto baud rate det. compelete Int. flag W1C     */
#define  UART_IDLE                  (1 << 12)                            /* USR2 Idle condition flag. Write 1 to clear           */
#define  UART_WAKE                  (1 <<  7)                            /* USR2 Wake flag, start bit detected. W1C              */
#define  UART_RTSF                  (1 <<  4)                            /* USR2 RTS triggered Int. Flag, Write 1 to clear       */
#define  UART_BRCD                  (1 <<  2)                            /* USR2 Break condition flag. Write 1 to clear          */
#define  UART_ORE                   (1 <<  1)                            /* USR2 Overrun condition flag. Write 1 to clear        */

                                                                         /* MMC / SD HC card definitions                         */
#define  SDHC1_EN                   (1 <<  9)                            /* PCCR0, Enable clock source for MMC / SD  HC          */
#define  CARD_PRESENCE              (1 << 15)                            /* Bit 15 in STATUS indicating presence of SD/MMC card  */
#define  START_CLK                  (1 <<  1)                            /* Bit 1 in STR_STP_CLK, enables the MMC/SD clock src   */
#define  STOP_CLK                   (1 <<  0)                            /* Bit 0 in STR_STP_CLK, disables the MMC/SD clock src  */

                                                                         /* CSPI3 (attached to MMC/SD HC                         */
#define  CSPI3_EN                   (1 << 23)                            /* PCCR1, Enable clock source for CSPI3                 */
#define  SWAP                       (1 << 21)                            /* ControlReg3, SWAP data between Tx and Rx FIFO's = 1  */
#define  BURST                      (1 << 23)                            /* ControlReg3, BURST                                   */
#define  SDHC_SPIEN                 (1 << 22)                            /* ControlReg3, SDHC SPI Mode Enable = 1                */
#define  SPIEN                      (1 << 10)                            /* ControlReg3, CSPI Module En = 1, 0 flushes fifo's    */
#define  MODE                       (1 << 11)                            /* ControlReg3, CSPI Mode. 1=Master, 0=Slave            */
#define  CS                         (3 << 19)                            /* ControlReg3, Chip Select, pins 20:19 = 00 for CSPI3  */
#define  XCH                        (1 <<  9)                            /* ControlReg3, Initiate Exchange=1 0=Idle, auto clears */
#define  SSPOL                      (1 <<  8)                            /* ControlReg3, Chip Sel Polarity, 1=active high, 0=active low               */
#define  SSCTL                      (1 <<  7)                            /* ControlReg3, Chip Sel Wave Form Sel. 0=stay low between bursts, 1=toggle  */
#define  PHA                        (1 <<  6)                            /* ControlReg3, Clock/Data Phase Relationship. 0=phase0, 1=phase1            */
#define  POL                        (1 <<  5)                            /* ControlReg3, SCLK Polarity, 0=active high, 1=act low */
#define  RR                         (1 <<  4)                            /* INT3, RxFIFO data present when = 1                   */
#define  TF                         (1 <<  2)                            /* INT3, TxFIFO full flag. full = 1.                    */

                                                                         /* GPIO                                                 */
#define  GPIO_EN                    (1 << 11)                            /* PCCR0, GPIO Clock Enable. 0=disabled, 1=enabled      */
#endif