📄 imx21-registers.h
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#ifndef _IMX21_REGISTERS_H
#define _IMX21_REGISTERS_H
/*
*********************************************************************************************************
* Philips LPC210x
* LPC210x Kick Start Card Board Support Package
*
* (c) Copyright 2004, Micrium, Weston, FL
* All Rights Reserved
*
*
* File : iMX21-Registers.h
* By : Eric Shufro
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* Register Definitions
*********************************************************************************************************
*/
/* AITC */
#define INCNTL (*((INT32U *)0x10040000)) /* Interrupt control register, ptr to vec table if md=1 */
#define NIMASK (*((INT32U *)0x10040004)) /* Interrupt Mask, disable int's with prio < mask */
#define INTENNUM (*((INT32U *)0x10040008)) /* Interrupt enable register */
#define INTDISNUM (*((INT32U *)0x1004000C)) /* Interrupt disable register */
#define INTENABLEH (*((INT32U *)0x10040010)) /* Interrupt enable register high */
#define INTENABLEL (*((INT32U *)0x10040014)) /* Interrupt enable register low */
#define INTTYPEH (*((INT32U *)0x10040018)) /* Interrupt type select high. norm/fast? */
#define INTTYPEL (*((INT32U *)0x1004001C)) /* Interrupt type select low. norm/fast? */
#define NIVECSR (*((INT32U *)0x10040040)) /* Normal interrupt vector register, by vector index. */
#define FIVECSR (*((INT32U *)0x10040044)) /* Fast interrupt vector register, by vector index. */
#define INTSRCH (*((INT32U *)0x10040048)) /* Interrupt source register high */
#define INTSRCL (*((INT32U *)0x1004004C)) /* Interrupt source register low */
/* GPT1, for OS ticker */
#define GPT1_TCTL1 (*((INT32U *)0x10003000)) /* GPT Control Register 1 */
#define GPT1_TPRER1 (*((INT32U *)0x10003004)) /* GPT Prescaler Register 1 */
#define GPT1_TCMP1 (*((INT32U *)0x10003008)) /* 11 BIT GPT Compare Register 1 */
#define GPT1_TCN1 (*((INT32U *)0x10003010)) /* GPT Counter Register 1 */
#define GPT1_TSTAT1 (*((INT32U *)0x10003014)) /* GPT Status Register 1 */
/* Optional GPT2, for OSView */
#define GPT2_TCTL1 (*((INT32U *)0x10004000)) /* GPT Control Register 1 */
#define GPT2_TPRER1 (*((INT32U *)0x10004004)) /* GPT Prescaler Register 1 */
#define GPT2_TCMP1 (*((INT32U *)0x10004008)) /* 11 BIT GPT Compare Register 1 */
#define GPT2_TCN1 (*((INT32U *)0x10004010)) /* GPT Counter Register 1 */
#define GPT2_TSTAT1 (*((INT32U *)0x10004014)) /* GPT Status Register 1 */
/* PLL Registers */
#define CSCR (*((INT32U *)0x10027000)) /* Clock Source Control Register */
#define MPCTL0 (*((INT32U *)0x10027004)) /* MPLL Control Register 0 */
#define MPCTL1 (*((INT32U *)0x10027008)) /* MPLL Control Register 1 */
#define SPCTL0 (*((INT32U *)0x1002700C)) /* Serial Peripheral PLL Control Register 0 */
#define SPCTL1 (*((INT32U *)0x10027010)) /* Serial Peripheral PLL Control Register 1 */
/* Peripheral Clock Registers */
#define PCDR0 (*((INT32U *)0x10027018)) /* Peripheral Clock Divider Register 0 */
#define PCDR1 (*((INT32U *)0x1002701C)) /* Peripheral Clock Divider Register 1 */
#define PCCR0 (*((INT32U *)0x10027020)) /* Peripheral Clock Control Register 0 */
#define PCCR1 (*((INT32U *)0x10027024)) /* Peripheral Clock Control Register 1 */
#define CCSR (*((INT32U *)0x10027028)) /* Clock Control Status Register */
/* Extended IO */
#define ExtendedIO (*((INT16U *)0xCC800000)) /* 16 bit data bus (LED's) */
/* GPIO, used for CS8900A Int pin, Port E, pin 11, RTS */
/* ... and for bit banging the MMC/SD card slot lines */
#define PTE_DDIR (*((INT32U *)0x10015400)) /* Port E, Data Direction Register */
#define PTE_OCR1 (*((INT32U *)0x10015404)) /* Output Configuration Register 1 */
#define PTE_0CR2 (*((INT32U *)0x10015408)) /* Output Configuration Register 2 */
#define PTE_ICONFA1 (*((INT32U *)0x1001540C)) /* Input Configuration Register A1 */
#define PTE_ICONFA2 (*((INT32U *)0x10015410)) /* Input Configuration Register A2 */
#define PTE_DR (*((INT32U *)0x1001541C)) /* Port E Data Register */
#define PTE_GIUS (*((INT32U *)0x10015420)) /* Port E, GPIO In Use Register, [23:18] = 0 for CSPI3 */
#define PTE_SSR (*((INT32U *)0x10015424)) /* Port E, Sample Status (IO Data Input) Register */
#define PTE_ICR1 (*((INT32U *)0x10015428)) /* Port E, Gen. Purpose Int Ctl Reg 1 */
#define PTE_ICR2 (*((INT32U *)0x1001542C)) /* Port E, Gen. Purpose Int Ctl Reg 2 */
#define PTE_IMR (*((INT32U *)0x10015430)) /* Port E, Gen. Purpose Int Mask Reg */
#define PTE_ISR (*((INT32U *)0x10015434)) /* Port E, Gen. Purpose Int Stat Reg */
#define PTE_GPR (*((INT32U *)0x10015438)) /* Port E, Gen. Purp. Reg. Sets Alt func for CSPI3 pins */
/* UART Registers for OS-View */
#define URXD_1 (*((INT32U *)0x1000A000)) /* UART1 Receiver Register */
#define UTXD_1 (*((INT32U *)0x1000A040)) /* UART1 Transmitter Register */
#define UCR1_1 (*((INT32U *)0x1000A080)) /* UART1 Control Register 1 */
#define UCR2_1 (*((INT32U *)0x1000A084)) /* UART1 Control Register 2 */
#define UCR3_1 (*((INT32U *)0x1000A088)) /* UART1 Control Register 3 */
#define UCR4_1 (*((INT32U *)0x1000A08C)) /* UART1 Control Register 4 */
#define UFCR_1 (*((INT32U *)0x1000A090)) /* UART1 FIFO Control Register */
#define USR1_1 (*((INT32U *)0x1000A094)) /* UART1 Status Register 1 */
#define USR2_1 (*((INT32U *)0x1000A098)) /* UART1 Status Register 2 */
#define UBIR_1 (*((INT32U *)0x1000A0A4)) /* UART1 BRM Incremental Register */
#define UBMR_1 (*((INT32U *)0x1000A0A8)) /* UART1 BRM Modulator Register */
#define UBRC_1 (*((INT32U *)0x1000A0AC)) /* UART1 Baud Rate Count Register */
#define ONEMS_1 (*((INT32U *)0x1000A0B0)) /* UART1 One Millisecond Register */
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