ra_alpha.h

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/*
 * ra_alpha.h: PT Rotalign Alpha
 *
 * Based on csir_ims.h
 *
 * Copyright (C) 2001  Erik Mouw ([e-mail])
 * Copyright (C) 2002  Holger Schurig <[e-mail]>
 * Copyright (C) 2002  Jeff Sutherland <[e-mail]>
 * Copyright (C) 2003  Abraham vd Merwe <[e-mail]>
 * Copyright (C) 2003  Stefan Eletzhofer <[e-mail]>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#ifndef BLOB_ARCH_RA_ALPHA_H
#define BLOB_ARCH_RA_ALPHA_H

#define USE_SERIAL1
#define TERMINAL_SPEED baud_115200

#define LED_GPIO		(GPIO_bit(0))

/* the base address were BLOB is loaded by the first stage loader */
#define BLOB_ABS_BASE_ADDR	(0xa0200400)

/* where do various parts live in RAM */
#define BOOT_PARAMS			(0xa0000100)
#define BLOB_RAM_BASE		(0xa0100000)
#define PARAM_RAM_BASE		(0xa0200000)
#define KERNEL_RAM_BASE		(0xa0800000)
#define RAMDISK_RAM_BASE	(0xa1000000)

/* and where do they live in flash */
#define BLOB_FLASH_BASE		(0x00000000)
#define BLOB_FLASH_LEN		(256 * 1024)
#define PARAM_FLASH_BASE	(0x00040000)
#define PARAM_FLASH_LEN		(256 * 1024)
#define CONFIG_FLASH_BASE	(0x00040000)
#define CONFIG_FLASH_LEN	(256 * 1024)
#define KERNEL_FLASH_BASE	(0x00080000)
#define KERNEL_FLASH_LEN	(1024 * 1024)
#define LOAD_RAMDISK		1 /* load ramdisk into ram */
#define RAMDISK_FLASH_BASE	(0x00180000)
#define RAMDISK_FLASH_LEN	(1536 * 1024)
#define ROOTFS_FLASH_BASE	(0x00300000)
#define ROOTFS_FLASH_LEN	(0x00600000) /* 6M */
#define DATAFS_FLASH_BASE	(0x00900000)
#define DATAFS_FLASH_LEN	(0x00700000) /* 7M */

/* this needs to be defined if you want parameter block support */
// #define PARAM_START PARAM_FLASH_BASE
// #define PARAM_LEN PARAM_FLASH_LEN

/* load ramdisk into ram */
#define LOAD_RAMDISK		1

/* RAM pool for up/downloading */
#define RAM_START			(0xa2000000)
#define RAM_SIZE			(16*1024*1024)

/* the size (in kbytes) to which the compressed ramdisk expands */
#define RAMDISK_SIZE		(4 * 1024)

#if 1 /* Full Speed */
//# define MDREFR_VALUE	0x0009f018
//# define MDCNFG_VALUE	0x000019c9
# define MDCNFG_VALUE	( MDCNFG_DE0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | \
						  MDCNFG_DNB0 | MDCNFG_DTC0(1) | MDCNFG_DLATCH0	| \
						  MDCNFG_DSA1111_0 )
# define MDREFR_VALUE	( MDREFR_DRI(24) | MDREFR_E0PIN | MDREFR_K0RUN | \
 						  MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN | \
 						  MDREFR_K2DB2 )
#define MDMRS_VALUE		0x00020002
/* L=27, M=4, N=1 */
#define CCCR_VALUE		( CCCR_L(1) | CCCR_M(3) | CCCR_N(2) )
#else /* SDRAM at half speed */
# define MDCNFG_VALUE	( MDCNFG_DE0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | \
						  MDCNFG_DNB0 | MDCNFG_DTC0(1) )
# define MDREFR_VALUE	( MDREFR_DRI(24) | MDREFR_E0PIN | MDREFR_K0RUN | \
 						  MDREFR_K0DB2 | MDREFR_E1PIN | MDREFR_K1RUN | \
 						  MDREFR_K1DB2 | MDREFR_K2DB2 )
# define MDMRS_VALUE	0x00020002
#endif

/*
 * RotAlign CPLD registers
 */
#define RA_CPLD_BASE	(PXA_CS2_PHYS)
#define RA_CTRL0		(RA_CPLD_BASE + 0x90)
#define RA_CTRL1		(RA_CPLD_BASE + 0xA0)

/* CTRL0 */
#define RA_CTRL0_USBSLAVE	( 1<<0 )
#define RA_CTRL0_X1			( 1<<1 )
#define RA_CTRL0_X2			( 1<<2 )
#define RA_CTRL0_nLAN_EN	( 1<<3 )
#define RA_CTRL0_X4			( 1<<4 )
#define RA_CTRL0_X5			( 1<<5 )
#define RA_CTRL0_X6			( 1<<6 )
#define RA_CTRL0_LCD_EN		( 1<<7 )


/* CTRL 1 */
#define RA_CTRL1_RS3_MUX(x) 	( (((u_char)x)&0x03)<<0 )
#define RA_CTRL1_RS3_MUX0	( 1<<0 )
#define RA_CTRL1_RS3_MUX1	( 1<<1 )
#define RA_CTRL1_nSRST		( 1<<2 )
#define RA_CTRL1_RS3_RS485_TERM	( 1<<3 )
#define RA_CTRL1_BEEP		( 1<<4 )
#define RA_CTRL1_LCD_POWER	( 1<<5 )
#define RA_CTRL1_6		( 1<<6 )
#define RA_CTRL1_7		( 1<<7 )

/* Some shorthand macros */
#define MEM( x )        (*((u32 *)(x)))
#define SET(reg,bit)	((reg) |= (1<<(bit)))
#define RST(reg,bit)	((reg) &= ~(1<<(bit)))

/* GPIO configuration */
#define GPIO0_VALUE	GPIO_OUT_LO
#define GPIO1_VALUE	GPIO_OUT_LO
#define GPIO2_VALUE	GPIO_INPUT			/* IRQ CPLD */
#define GPIO3_VALUE	GPIO_INPUT			/* USB IRQ */
#define GPIO4_VALUE	GPIO_INPUT			/* LAN IRQ (neg) */
#define GPIO5_VALUE	GPIO_INPUT			/* CF IRQ (neg) */
#define GPIO6_VALUE	GPIO_INPUT			/* nUSB_H_OVERCURRENT */
#define GPIO7_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN1)	/* 48MHz Clock Out for CPLD */
#define GPIO8_VALUE	GPIO_INPUT			/* OnOff KBD */
#define GPIO9_VALUE	GPIO_OUT_LO
#define GPIO10_VALUE	GPIO_OUT_LO
#define GPIO11_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN1)	/* 3.6 MHz Clock out */
#define GPIO12_VALUE	GPIO_OUT_LO
#define GPIO13_VALUE	GPIO_OUT_LO
#define GPIO14_VALUE	GPIO_OUT_LO
#define GPIO15_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nCS1 */
#define GPIO16_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD Contrast PWM */
#define GPIO17_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD Bright PWM */
#define GPIO18_VALUE	GPIO_INPUT			/* RDY LAN	*/
#define GPIO19_VALUE	GPIO_OUT_LO
#define GPIO20_VALUE	GPIO_OUT_LO
#define GPIO21_VALUE	GPIO_OUT_LO
#define GPIO22_VALUE	GPIO_OUT_LO
#define GPIO23_VALUE	GPIO_OUT_LO
#define GPIO24_VALUE	GPIO_OUT_LO
#define GPIO25_VALUE	GPIO_OUT_LO
#define GPIO26_VALUE	GPIO_OUT_LO
#define GPIO27_VALUE	GPIO_OUT_LO
#define GPIO28_VALUE	GPIO_OUT_LO
#define GPIO29_VALUE	GPIO_OUT_LO
#define GPIO30_VALUE	GPIO_OUT_LO
#define GPIO31_VALUE	GPIO_OUT_LO
#define GPIO32_VALUE	GPIO_OUT_LO
#define GPIO33_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nCS5 */
#define GPIO34_VALUE	(GPIO_INPUT|GPIO_ALT_FN1)	/* FFRXD */
#define GPIO35_VALUE	GPIO_OUT_HI 			/* Core Fast 1 */
#define GPIO36_VALUE	GPIO_OUT_HI 			/* Core Fast 2 */
#define GPIO37_VALUE	GPIO_OUT_LO			/* n3V3_En */
#define GPIO38_VALUE	GPIO_OUT_LO			/* n5V4_En */
#define GPIO39_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* FFTXD */
#define GPIO40_VALUE	GPIO_OUT_HI			/* nUSB_H_ON */
#define GPIO41_VALUE	GPIO_OUT_LO			/* CF_RST */
#define GPIO42_VALUE	(GPIO_INPUT|GPIO_ALT_FN1)
#define GPIO43_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)
#define GPIO44_VALUE	(GPIO_INPUT|GPIO_ALT_FN1)
#define GPIO45_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)
#define GPIO46_VALUE	(GPIO_INPUT|GPIO_ALT_FN2)
#define GPIO47_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN1)
#define GPIO48_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nPOE */
#define GPIO49_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nPWE */
#define GPIO50_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nPIOR */
#define GPIO51_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nPIOW */
#define GPIO52_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nPCE1 */
#define GPIO53_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nPCE2 */
#define GPIO54_VALUE	GPIO_OUT_HI			/* nPKTSEL */
#define GPIO55_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nPREG */
#define GPIO56_VALUE	(GPIO_INPUT|GPIO_ALT_FN1)	/* nPWAIT */
#define GPIO57_VALUE	(GPIO_INPUT|GPIO_ALT_FN1)	/* nIOIS16 */
#define GPIO58_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD D0..7 */
#define GPIO59_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD D0..7 */
#define GPIO60_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD D0..7 */
#define GPIO61_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD D0..7 */
#define GPIO62_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD D0..7 */
#define GPIO63_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD D0..7 */
#define GPIO64_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD D0..7 */
#define GPIO65_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD D0..7 */
#define GPIO66_VALUE	GPIO_OUT_LO
#define GPIO67_VALUE	GPIO_OUT_LO
#define GPIO68_VALUE	GPIO_OUT_LO
#define GPIO69_VALUE	GPIO_OUT_LO
#define GPIO70_VALUE	GPIO_OUT_LO
#define GPIO71_VALUE	GPIO_OUT_LO
#define GPIO72_VALUE	GPIO_OUT_LO
#define GPIO73_VALUE	GPIO_OUT_LO
#define GPIO74_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD FCLK */
#define GPIO75_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD LCLK */
#define GPIO76_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD PCLK */
#define GPIO77_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN2)	/* LCD BIAS */
#define GPIO78_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nCS2 */
#define GPIO79_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nCS3 */
#define GPIO80_VALUE	(GPIO_OUT_HI|GPIO_ALT_FN2)	/* nCS4 */
#define GPIO81_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN1)	/* BT SCLK */
#define GPIO82_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN1)	/* BT SFRM */
#define GPIO83_VALUE	(GPIO_OUT_LO|GPIO_ALT_FN1)	/* BT MOSI */
#define GPIO84_VALUE	(GPIO_INPUT |GPIO_ALT_FN2)	/* BT MISO */
#define GPIO85_VALUE	GPIO_OUT_HI			/* nMSP_RST */

#endif	/* #ifndef BLOB_ARCH_RA_ALPHA_H */