pj.h

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/* Definitions of target machine for GNU compiler for picoJava
   Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.

This file is part of GNU CC.

GNU CC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.

GNU CC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with GNU CC; see the file COPYING.  If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA.  */

/* Contributed by Steve Chamberlain of Transmeta ([e-mail]).  */


#define TARGET_VERSION  fputs ("(picoJava)", stderr);

/* We support two different default configurations.  */
#undef ASM_SPEC
#ifdef TARGET_LITTLE_ENDIAN_DEFAULT
#define CPP_SPEC        "%{mb:-D__BIG_ENDIAN__ }%{!mb:-D__LITTLE_ENDIAN__ }" 
#define ASM_SPEC        "%{mb:-EB }%{!mb:-EL }"
#else
#define CPP_SPEC        "%{ml:-D__LITTLE_ENDIAN__ }%{!ml:-D__BIG_ENDIAN__}"
#define ASM_SPEC        "%{ml:-EL } %{!ml:-EB }"
#endif

#ifndef CPP_PREDEFINES
#define CPP_PREDEFINES "-D__ELF__ -D__pj__ -Asystem=posix"
#endif

/* Run-time compilation parameters selecting different hardware subsets.  */

extern int target_flags;

#define LITTLE_ENDIAN_BIT (1<<0)
#define EXTENSIONS_BIT    (1<<1)
#define PJ_TEST_BIT       (1<<2)
#define REORG_BIT         (1<<3)

/* Nonzero if generating code for a little endian pico java.  */

#define TARGET_LITTLE_ENDIAN     (target_flags & LITTLE_ENDIAN_BIT)

/* Nonzero to turn on internal tests.  */

#define TARGET_TEST              (target_flags & PJ_TEST_BIT)

/* Nonzero to turn on picoJava extensions.  */

#define TARGET_TM_EXTENSIONS     (target_flags & EXTENSIONS_BIT)

/* Nonzero to turn on the reorganization pass.  */

#define TARGET_REORG             (target_flags & REORG_BIT)

#ifdef TARGET_LITTLE_ENDIAN_DEFAULT
#define TARGET_DEFAULT  (LITTLE_ENDIAN_BIT|EXTENSIONS_BIT|REORG_BIT)
#else
#define TARGET_DEFAULT  REORG_BIT
#endif

#define TARGET_SWITCHES  \
{ {"l",         LITTLE_ENDIAN_BIT,			\
   N_("Generate little endian data")           },	\
  {"b",        -LITTLE_ENDIAN_BIT,			\
   N_("Generate big endian data")              },	\
  {"t",         PJ_TEST_BIT,				\
   N_("Turn on maintainer testing code")       },	\
  {"ext",       EXTENSIONS_BIT,				\
   N_("Enable Transmeta picoJava extensions")  },	\
  {"no-ext",   -EXTENSIONS_BIT,				\
   N_("Disable Transmeta picoJava extensions") },	\
  {"no-reorg", -REORG_BIT,				\
   N_("Disable reorganization pass")           },	\
  {"",          TARGET_DEFAULT,    0 }}

/* Sometimes certain combinations of command options do not make
   sense on a particular target machine.  You can define a macro
   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
   defined, is executed once just after all the command options have
   been parsed.

   Don't use this macro to turn on various extra optimizations for
   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  

   We take this chance to register the global variables with the garbage
   collector. */

#define OVERRIDE_OPTIONS                                                \
 do {                                                                   \
   ggc_add_rtx_root (&pj_cmp_op0, 1);                                   \
   ggc_add_rtx_root (&pj_cmp_op1, 1);                                   \
 } while (0)

/* Define this to change the optimizations performed by default.  */
#define OPTIMIZATION_OPTIONS(LEVEL,SIZE)                                \
 do {                                                                   \
   if (optimize)                                                        \
       flag_force_addr = 1;                                             \
 } while (0)

/* Target machine storage layout.  */

/* Define to use software floating point emulator for REAL_ARITHMETIC and
   decimal <-> binary conversion.  */
#define REAL_ARITHMETIC

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN  0

/* Define this if most significant byte of a word is the lowest numbered.  */
#define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)

/* Define this if most significant word of a multiword number is the lowest
   numbered.  */
#define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)

/* Define this to set the endianness to use in libgcc2.c, which can
   not depend on target_flags.  */
#if defined(TARGET_LITTLE_ENDIAN_DEFAULT)
#define LIBGCC2_WORDS_BIG_ENDIAN 0
#else
#define LIBGCC2_WORDS_BIG_ENDIAN 1
#endif

/* Number of bits in an addressable storage unit.  */
#define BITS_PER_UNIT  8

/* Width in bits of a "word", which is the contents of a machine register.
   Note that this is not necessarily the width of data type `int';
   if using 16-bit ints on a 68000, this would still be 32.
   But on a machine with 16-bit registers, this would be 16.  */
#define BITS_PER_WORD  32
#define MAX_BITS_PER_WORD 32

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD  4

/* Width in bits of a pointer.
   See also the macro `Pmode' defined below.  */
#define POINTER_SIZE  32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY   32

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY  32

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY  8

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY  32

/* No data type wants to be aligned rounder than this.  */
#define BIGGEST_ALIGNMENT  32

/* The best alignment to use in cases where we have a choice.  */
#define FASTEST_ALIGNMENT 32

/* Make strings word-aligned so strcpy from constants will be faster.  */
#define CONSTANT_ALIGNMENT(EXP, ALIGN)  \
  ((TREE_CODE (EXP) == STRING_CST       \
    && (ALIGN) < FASTEST_ALIGNMENT)     \
    ? FASTEST_ALIGNMENT : (ALIGN))

/* Make arrays of chars word-aligned for the same reasons.  */
#define DATA_ALIGNMENT(TYPE, ALIGN)             \
  (TREE_CODE (TYPE) == ARRAY_TYPE               \
   && TYPE_MODE (TREE_TYPE (TYPE)) == QImode    \
   && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN))

/* Set this non-zero if move instructions will actually fail to work
   when given unaligned data.  */
#define STRICT_ALIGNMENT 1


/* Standard register usage.  */

/* Enumerate the hardware registers.  */

enum
{
  R0_REG,       R1_REG,         R2_REG,         R3_REG, 
  R4_REG,       R5_REG,         R6_REG,         R7_REG, 
  R8_REG,       R9_REG,         R10_REG,        R11_REG,
  R12_REG,      R13_REG,        R14_REG,        R15_REG,

  R16_REG,      R17_REG,        R18_REG,        R19_REG,
  R20_REG,      R21_REG,        R22_REG,        R23_REG,
  R24_REG,      R25_REG,        R26_REG,        R27_REG,
  R28_REG,      R29_REG,        R30_REG,        R31_REG,

  I0_REG,       I1_REG,         I2_REG,         I3_REG,  
  I4_REG,       I5_REG,         I6_REG,         I7_REG,  
  I8_REG,       I9_REG,         I10_REG,        I11_REG, 
  I12_REG,      I13_REG,        I14_REG,        I15_REG, 

  I16_REG,      I17_REG,        I18_REG,        I19_REG, 
  I20_REG,      I21_REG,        I22_REG,        I23_REG, 
  I24_REG,      I25_REG,        I26_REG,        I27_REG, 
  I28_REG,      I29_REG,        I30_REG,        ISC_REG, 

  G0_REG,       G1_REG,         G2_REG,         G3_REG,  
  G4_REG,       G5_REG,         G6_REG,         G7_REG,  
  VARS_REG,     OPTOP_REG,      SC_REG,         PC_REG,  
  TICKS_REG,    SLOW_REG,       VA_REG,         D3_REG, 

  D4_REG,       D5_REG,         D6_REG,         D7_REG,
  Q0_REG,       Q1_REG,         Q2_REG,         Q3_REG,
  P0_REG,       P1_REG,         P2_REG,         P3_REG,
  P4_REG,       P5_REG,         P6_REG,         P7_REG,

  O0_REG,       O1_REG,         O2_REG,         O3_REG, 
  O4_REG,       O5_REG,         O6_REG,         O7_REG, 
  O8_REG,       O9_REG,         O10_REG,        O11_REG,
  O12_REG,      O13_REG,        O14_REG,        O15_REG,

  O16_REG,      O17_REG,        O18_REG,        O19_REG,
  O20_REG,      O21_REG,        O22_REG,        O23_REG,
  O24_REG,      O25_REG,        O26_REG,        O27_REG,
  O28_REG,      O29_REG,        O30_REG,        OSC_REG,
  
  LAST_O_REG=OSC_REG,
  LAST_R_REG=R31_REG,
  LAST_I_REG=ISC_REG,
  LAST_S_REG=P7_REG

};

/* Useful predicates.  */

#define STACK_REGNO_P(REGNO) 		\
	(((unsigned) (REGNO)) <= LAST_I_REG)

#define OUTGOING_REGNO_P(REGNO) 	\
  	(((REGNO) >= O0_REG) && ((REGNO) <= LAST_O_REG))

#define INCOMING_REGNO_P(REGNO)   	\
	(((REGNO) >= I0_REG) && ((REGNO) <= LAST_I_REG))

#define STACK_REG_RTX_P(RTX)    	\
	(GET_CODE (RTX) == REG && STACK_REGNO_P (REGNO (RTX)))

#define OUTGOING_REG_RTX_P(RTX) 	\
	(GET_CODE (RTX) == REG && OUTGOING_REGNO_P (REGNO (RTX)))

#define OPTOP_REG_RTX_P(RTX) 		\
	(GET_CODE (RTX) == REG && REGNO (RTX) == OPTOP_REG)

#define FIRST_PSEUDO_REGISTER 128

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.  */

#define FIXED_REGISTERS                                                 \
 {                                                                      \
   0,0,0,0, 0,0,0,0,  /* r0 .. r7  */                                   \
   0,0,0,0, 0,0,0,0,  /* r8 .. r15 */                                   \
   0,0,0,0, 0,0,0,0,  /* r16.. r23 */                                   \
   0,0,0,0, 0,0,0,0,  /* r24.. r31 */                                   \
                                                                        \
   0,0,0,0, 0,0,0,0,  /* i0 .. i7  */                                   \
   0,0,0,0, 0,0,0,0,  /* i8 .. i15 */                                   \
   0,0,0,0, 0,0,0,0,  /* i16.. i23 */                                   \
   0,0,0,0, 0,0,0,0,  /* i24.. i31 */                                   \
                                                                        \
   1,0,0,1, 1,1,1,1,  /* g0 .. g7  */                                   \
   1,1,1,1, 1,1,1,1,  /* vars, optop, sc, pc, ticks, slow, va, sgo */   \
   1,1,1,1, 1,1,1,1,  /* d4 d5 d6 ap p0 p1 p2 p3 */                     \
   1,1,1,1, 1,1,1,1,  /* q1 .. q7 */                                    \
                                                                        \
   0,0,0,0, 0,0,0,0,  /* o0 .. o7  */                                   \
   0,0,0,0, 0,0,0,0,  /* o8 .. o15 */                                   \
   0,0,0,0, 0,0,0,0,  /* o16.. o23 */                                   \
   0,0,0,0, 0,0,0,0 } /* o24.. o31 */                                   
                                                                          

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  

   We pretend that some standard registers are call clobbered so the
   exception handler code has somewhere to play.  */

#define CALL_USED_REGISTERS                                             \
 {                                                                      \
   0,0,0,0, 0,0,0,0,  /* r0 ..r7  */                                    \
   0,0,0,0, 0,0,0,0,  /* r8 ..r15 */                                    \
   0,0,0,0, 1,1,1,1,  /* r16..r23 */                                    \
   1,1,1,1, 1,1,1,1,  /* r24..r31 */                                    \
                                                                        \
   0,0,0,0, 0,0,0,0,  /* i0 ..i7  */                                    \
   0,0,0,0, 0,0,0,0,  /* i8 ..i15 */                                    \
   0,0,0,0, 0,0,0,0,  /* i16..i23 */                                    \
   0,0,0,0, 0,0,0,0,  /* i24..i31 */                                    \
                                                                        \
   1,1,1,1, 0,0,0,0,  /* g0 ..g7  */                                    \
   1,1,1,1, 1,1,1,1,  /* vars, optop, sc, pc, ticls, slow, va, sgo */   \
   1,1,1,1, 1,1,1,1,  /* d4 d5 d6 ap p0..p3*/                           \
   1,1,1,1, 1,1,1,1,  /* q0..q7  */                                     \
                                                                        \
   1,1,1,1, 1,1,1,1,  /* o0 ..o7  */                                    \
   1,1,1,1, 1,1,1,1,  /* o8 ..o15 */                                    \
   1,1,1,1, 1,1,1,1,  /* o16..o23 */                                    \
   1,1,1,1, 1,1,1,1 } /* o24..o31 */                                    
  
/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.  */