c4x.h

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/* Definitions of target machine for GNU compiler.  TMS320C[34]x
   Copyright (C) 1994, 1995, 1996, 1997, 1998,
   1999, 2000, 2001, 2002 Free Software Foundation, Inc.

   Contributed by Michael Hayes ([e-mail])
              and Herman Ten Brugge ([e-mail]).

   This file is part of GNU CC.

   GNU CC is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2, or (at your option)
   any later version.

   GNU CC is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GNU CC; see the file COPYING.  If not, write to
   the Free Software Foundation, 59 Temple Place - Suite 330,
   Boston, MA 02111-1307, USA.  */

#include "hwint.h"

/* RUN-TIME TARGET SPECIFICATION.  */

#define C4x   1

/* Name of the c4x assembler.  */

#define ASM_PROG "c4x-as"

/* Name of the c4x linker.  */

#define LD_PROG "c4x-ld"

/* Define assembler options.  */

#define ASM_SPEC "\
%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
%{!m30:%{!m40:-m40}}}}}}}} \
%{mcpu=30:-m30} \
%{mcpu=31:-m31} \
%{mcpu=32:-m32} \
%{mcpu=33:-m33} \
%{mcpu=40:-m40} \
%{mcpu=44:-m44} \
%{m30:-m30} \
%{m31:-m31} \
%{m32:-m32} \
%{m33:-m33} \
%{m40:-m40} \
%{m44:-m44} \
%{mmemparm:-p} %{mregparm:-r} \
%{!mmemparm:%{!mregparm:-r}} \
%{mbig:-b} %{msmall:-s} \
%{!msmall:%{!mbig:-b}}"

/* Define linker options.  */

#define LINK_SPEC "\
%{m30:--architecture c3x} \
%{m31:--architecture c3x} \
%{m32:--architecture c3x} \
%{m33:--architecture c3x} \
%{mcpu=30:--architecture c3x} \
%{mcpu=31:--architecture c3x} \
%{mcpu=32:--architecture c3x} \
%{mcpu=33:--architecture c3x}"

/* Define C preprocessor options.  */

#define CPP_SPEC "\
%{!m30:%{!m31:%{!m32:%{!m33:%{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:\
%{!mcpu=40:%{!mcpu=44:%{\
!m40:%{!m44:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40}}}}}}}}}}}} \
%{mcpu=30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
%{m30:-D_TMS320C3x -D_C3x -D_TMS320C30 -D_C30 } \
%{mcpu=31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
%{m31:-D_TMS320C3x -D_C3x -D_TMS320C31 -D_C31 } \
%{mcpu=32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
%{m32:-D_TMS320C3x -D_C3x -D_TMS320C32 -D_C32 } \
%{mcpu=33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
%{m33:-D_TMS320C3x -D_C3x -D_TMS320C33 -D_C33 } \
%{mcpu=40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
%{m40:-D_TMS320C4x -D_C4x -D_TMS320C40 -D_C40 } \
%{mcpu=44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
%{m44:-D_TMS320C4x -D_C4x -D_TMS320C44 -D_C44 } \
%{mmemparm:-U_REGPARM }%{mregparm:-D_REGPARM } \
%{!mmemparm:%{!mregparm:-D_REGPARM }} \
%{msmall:-U_BIGMODEL } %{mbig:-D_BIGMODEL } \
%{!msmall:%{!mbig:-D_BIGMODEL }} \
%{finline-functions:-D_INLINE }"

/* Specify the end file to link with.  */

#define ENDFILE_SPEC ""

/* Target compilation option flags.  */

#define SMALL_MEMORY_FLAG   0x0000001 /* Small memory model.  */
#define MPYI_FLAG           0x0000002 /* Use 24-bit MPYI for C3x.  */
#define FAST_FIX_FLAG       0x0000004 /* Fast fixing of floats.  */
#define RPTS_FLAG           0x0000008 /* Allow use of RPTS.  */
#define C3X_FLAG            0x0000010 /* Emit C3x code.  */
#define TI_FLAG             0x0000020 /* Be compatible with TI assembler.  */
#define PARANOID_FLAG       0x0000040 /* Be paranoid about DP reg. in ISRs.  */
#define MEMPARM_FLAG        0x0000080 /* Pass arguments on stack.  */
#define DEVEL_FLAG          0x0000100 /* Enable features under development.  */
#define RPTB_FLAG           0x0000200 /* Enable repeat block.  */
#define BK_FLAG             0x0000400 /* Use BK as general register.  */
#define DB_FLAG             0x0000800 /* Use decrement and branch for C3x.  */
#define DEBUG_FLAG          0x0001000 /* Enable debugging of GCC.  */
#define HOIST_FLAG          0x0002000 /* Force constants into registers.  */
#define LOOP_UNSIGNED_FLAG  0x0004000 /* Allow unsigned loop counters.  */
#define FORCE_FLAG          0x0008000 /* Force op0 and op1 to be same.  */
#define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats.  */
#define PARALLEL_INSN_FLAG  0x0020000 /* Allow parallel insns.  */
#define PARALLEL_MPY_FLAG   0x0040000 /* Allow MPY||ADD, MPY||SUB insns.  */
#define ALIASES_FLAG	    0x0080000 /* Assume mem refs possibly aliased.  */

#define C30_FLAG            0x0100000 /* Emit C30 code.  */
#define C31_FLAG            0x0200000 /* Emit C31 code.  */
#define C32_FLAG            0x0400000 /* Emit C32 code.  */
#define C33_FLAG            0x0400000 /* Emit C33 code.  */
#define C40_FLAG            0x1000000 /* Emit C40 code.  */
#define C44_FLAG            0x2000000 /* Emit C44 code.  */

/* Run-time compilation parameters selecting different hardware subsets.

   Macro to define tables used to set the flags.
   This is a list in braces of triplets in braces,
   each pair being { "NAME", VALUE, "DESCRIPTION" }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES							\
{ { "small", SMALL_MEMORY_FLAG,						\
    N_("Small memory model") },						\
  { "big", -SMALL_MEMORY_FLAG,						\
    N_("Big memory model") },						\
  { "mpyi", MPYI_FLAG,							\
    N_("Use MPYI instruction for C3x") },				\
  { "no-mpyi", -MPYI_FLAG,						\
    N_("Do not use MPYI instruction for C3x") },			\
  { "fast-fix", FAST_FIX_FLAG,						\
    N_("Use fast but approximate float to integer conversion") },	\
  { "no-fast-fix", -FAST_FIX_FLAG,					\
    N_("Use slow but accurate float to integer conversion") },		\
  { "rpts", RPTS_FLAG,							\
    N_("Enable use of RTPS instruction") },				\
  { "no-rpts", -RPTS_FLAG,						\
    N_("Disable use of RTPS instruction") },				\
  { "rptb", RPTB_FLAG,							\
    N_("Enable use of RTPB instruction") },				\
  { "no-rptb", -RPTB_FLAG,						\
    N_("Disable use of RTPB instruction") },				\
  { "30", C30_FLAG,							\
    N_("Generate code for C30 CPU")},					\
  { "31", C31_FLAG,							\
    N_("Generate code for C31 CPU")},					\
  { "32", C32_FLAG,							\
    N_("Generate code for C32 CPU")},					\
  { "33", C33_FLAG,							\
    N_("Generate code for C33 CPU")},					\
  { "40", C40_FLAG,							\
    N_("Generate code for C40 CPU")},					\
  { "44", C44_FLAG,							\
    N_("Generate code for C44 CPU")},					\
  { "ti", TI_FLAG,							\
    N_("Emit code compatible with TI tools")},				\
  { "no-ti", -TI_FLAG,							\
    N_("Emit code to use GAS extensions")},				\
  { "paranoid", PARANOID_FLAG,						\
    N_("Save DP across ISR in small memory model") },			\
  { "no-paranoid", -PARANOID_FLAG,					\
    N_("Don't save DP across ISR in small memory model") },		\
  { "isr-dp-reload", PARANOID_FLAG,					\
    N_("Save DP across ISR in small memory model") },			\
  { "no-isr-dp-reload", -PARANOID_FLAG,					\
    N_("Don't save DP across ISR in small memory model") },		\
  { "memparm", MEMPARM_FLAG,						\
    N_("Pass arguments on the stack") },				\
  { "regparm", -MEMPARM_FLAG,						\
    N_("Pass arguments in registers") },				\
  { "devel", DEVEL_FLAG,						\
    N_("Enable new features under development") },			\
  { "no-devel", -DEVEL_FLAG,						\
    N_("Disable new features under development") },			\
  { "bk", BK_FLAG,							\
    N_("Use the BK register as a general purpose register") },		\
  { "no-bk", -BK_FLAG,							\
    N_("Do not allocate BK register") },				\
  { "db", DB_FLAG,							\
    N_("Enable use of DB instruction") },				\
  { "no-db", -DB_FLAG,							\
    N_("Disable use of DB instruction") },				\
  { "debug", DEBUG_FLAG,						\
    N_("Enable debugging") },						\
  { "no-debug", -DEBUG_FLAG,						\
    N_("Disable debugging") },						\
  { "hoist", HOIST_FLAG,						\
    N_("Force constants into registers to improve hoisting") },		\
  { "no-hoist", -HOIST_FLAG,						\
    N_("Don't force constants into registers") },			\
  { "force", FORCE_FLAG,						\
    N_("Force RTL generation to emit valid 3 operand insns") },		\
  { "no-force", -FORCE_FLAG,						\
    N_("Allow RTL generation to emit invalid 3 operand insns") },	\
  { "loop-unsigned", LOOP_UNSIGNED_FLAG,				\
    N_("Allow unsigned interation counts for RPTB/DB") },		\
  { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG,				\
    N_("Disallow unsigned iteration counts for RPTB/DB") },		\
  { "preserve-float", PRESERVE_FLOAT_FLAG,				\
    N_("Preserve all 40 bits of FP reg across call") },			\
  { "no-preserve-float", -PRESERVE_FLOAT_FLAG,				\
    N_("Only preserve 32 bits of FP reg across call") },		\
  { "parallel-insns", PARALLEL_INSN_FLAG,				\
    N_("Enable parallel instructions") },				\
  { "no-parallel-insns", -PARALLEL_INSN_FLAG,				\
    N_("Disable parallel instructions") },				\
  { "parallel-mpy", PARALLEL_MPY_FLAG,					\
    N_("Enable MPY||ADD and MPY||SUB instructions") },			\
  { "no-parallel-mpy", -PARALLEL_MPY_FLAG,				\
    N_("Disable MPY||ADD and MPY||SUB instructions") },			\
  { "aliases", ALIASES_FLAG,						\
    N_("Assume that pointers may be aliased") },			\
  { "no-aliases", -ALIASES_FLAG,					\
    N_("Assume that pointers not aliased") },				\
  { "", TARGET_DEFAULT, ""} }

/* Default target switches.  */

/* Play safe, not the fastest code.  */
#define TARGET_DEFAULT		ALIASES_FLAG | PARALLEL_INSN_FLAG \
				| PARALLEL_MPY_FLAG | RPTB_FLAG

/* Caveats:
   Max iteration count for RPTB/RPTS is 2^31 + 1.
   Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
   RPTS blocks interrupts.  */


extern int target_flags;

#define TARGET_INLINE		(! optimize_size) /* Inline MPYI.  */
#define TARGET_SMALL_REG_CLASS	0

#define TARGET_SMALL		(target_flags & SMALL_MEMORY_FLAG)
#define TARGET_MPYI		(!TARGET_C3X || (target_flags & MPYI_FLAG))
#define TARGET_FAST_FIX		(target_flags & FAST_FIX_FLAG)
#define TARGET_RPTS		(target_flags & RPTS_FLAG)
#define TARGET_TI		(target_flags & TI_FLAG)
#define TARGET_PARANOID		(target_flags & PARANOID_FLAG)
#define TARGET_MEMPARM		(target_flags & MEMPARM_FLAG)
#define TARGET_DEVEL		(target_flags & DEVEL_FLAG)
#define TARGET_RPTB		(target_flags & RPTB_FLAG \
				 && optimize >= 2)
#define TARGET_BK		(target_flags & BK_FLAG)
#define TARGET_DB		(! TARGET_C3X || (target_flags & DB_FLAG))
#define TARGET_DEBUG		(target_flags & DEBUG_FLAG)
#define TARGET_HOIST		(target_flags & HOIST_FLAG)
#define TARGET_LOOP_UNSIGNED	(target_flags & LOOP_UNSIGNED_FLAG)
#define TARGET_FORCE		(target_flags & FORCE_FLAG)
#define	TARGET_PRESERVE_FLOAT	(target_flags & PRESERVE_FLOAT_FLAG)
#define TARGET_PARALLEL		((target_flags & PARALLEL_INSN_FLAG) \
				 && optimize >= 2)
#define TARGET_PARALLEL_MPY	(TARGET_PARALLEL \
				 && (target_flags & PARALLEL_MPY_FLAG))
#define	TARGET_ALIASES		(target_flags & ALIASES_FLAG)

#define TARGET_C3X		(target_flags & C3X_FLAG)
#define TARGET_C30		(target_flags & C30_FLAG)
#define TARGET_C31		(target_flags & C31_FLAG)
#define TARGET_C32		(target_flags & C32_FLAG)
#define TARGET_C33		(target_flags & C33_FLAG)
#define TARGET_C40		(target_flags & C40_FLAG)
#define TARGET_C44		(target_flags & C44_FLAG)

/* Define some options to control code generation.  */
#define TARGET_LOAD_ADDRESS	(1 || (! TARGET_C3X && ! TARGET_SMALL))
/* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
   during RTL generation.  */
#define TARGET_EXPOSE_LDP	0
/* Nonzero to force loading of direct memory references into a register.  */
#define TARGET_LOAD_DIRECT_MEMS	0

/* -mrpts            allows the use of the RPTS instruction irregardless.
   -mrpts=max-cycles will use RPTS if the number of cycles is constant
   and less than max-cycles.  */

#define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)

#define	BCT_CHECK_LOOP_ITERATIONS  !(TARGET_LOOP_UNSIGNED)

/* -mcpu=XX    with XX = target DSP version number.  */

extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;

#define TARGET_OPTIONS						\
{ {"rpts=", &c4x_rpts_cycles_string,				\
   N_("Specify maximum number of iterations for RPTS") },	\
  {"cpu=", &c4x_cpu_version_string,				\
   N_("Select CPU to generate code for") } }

/* Sometimes certain combinations of command options do not make sense
   on a particular target machine.  You can define a macro
   `OVERRIDE_OPTIONS' to take account of this.  This macro, if
   defined, is executed once just after all the command options have
   been parsed.  */

#define OVERRIDE_OPTIONS c4x_override_options ()

/* Define this to change the optimizations performed by default.  */

#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)

/* Run Time Target Specification.  */

#define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");

/* Storage Layout.  */

#define BITS_BIG_ENDIAN		0
#define BYTES_BIG_ENDIAN	0
#define WORDS_BIG_ENDIAN	0

/* Technically, we are little endian, but we put the floats out as
   whole longs and this makes GCC put them out in the right order.  */

#define FLOAT_WORDS_BIG_ENDIAN	1

/* Note the ANSI C standard requires sizeof(char) = 1.  On the C[34]x
   all integral and floating point data types are stored in memory as
   32-bits (floating point types can be stored as 40-bits in the
   extended precision registers), so sizeof(char) = sizeof(short) =
   sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1.  */

#define BITS_PER_UNIT		32
#define BITS_PER_WORD		32
#define UNITS_PER_WORD		1
#define POINTER_SIZE		32
#define PARM_BOUNDARY	        32
#define STACK_BOUNDARY		32
#define FUNCTION_BOUNDARY	32
#define BIGGEST_ALIGNMENT	32
#define EMPTY_FIELD_BOUNDARY	32
#define STRICT_ALIGNMENT	0
#define TARGET_FLOAT_FORMAT	C4X_FLOAT_FORMAT
#define MAX_FIXED_MODE_SIZE	64 /* HImode.  */

/* If a structure has a floating point field then force structure
   to have BLKMODE.  */
#define MEMBER_TYPE_FORCES_BLK(FIELD) \
  (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE)

/* Number of bits in the high and low parts of a two stage
   load of an immediate constant.  */
#define BITS_PER_HIGH 16
#define BITS_PER_LO_SUM 16