h8300.md

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  [(set_attr "length" "2")
   (set_attr "cc" "none_0hit")])

;; This is a "bridge" instruction.  Combine can't cram enough insns
;; together to crate a MAC instruction directly, but it can create
;; this instruction, which then allows combine to create the real
;; MAC insn.
;;
;; Unfortunately, if combine doesn't create a MAC instruction, this
;; insn must generate reasonably correct code.  Egad.
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=a")
	(mult:SI
	  (sign_extend:SI
	    (mem:HI (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
	  (sign_extend:SI
	    (mem:HI (post_inc:SI (match_operand:SI 2 "register_operand" "r"))))))]
  "TARGET_MAC"
  "clrmac\;mac	@%2+,@%1+"
  [(set_attr "length" "6")
   (set_attr "cc" "none_0hit")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=a")
	(plus:SI (mult:SI
	  (sign_extend:SI (mem:HI
	    (post_inc:SI (match_operand:SI 1 "register_operand" "r"))))
	  (sign_extend:SI (mem:HI
	    (post_inc:SI (match_operand:SI 2 "register_operand" "r")))))
	      (match_operand:SI 3 "register_operand" "0")))]
  "TARGET_MAC"
  "mac	@%2+,@%1+"
  [(set_attr "length" "4")
   (set_attr "cc" "none_0hit")])

;; ----------------------------------------------------------------------
;; DIVIDE/MOD INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "udivmodqi4"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI
	  (udiv:HI
	    (match_operand:HI 1 "register_operand" "0")
	    (zero_extend:HI (match_operand:QI 2 "register_operand" "r")))))
   (set (match_operand:QI 3 "register_operand" "=r")
	(truncate:QI
	  (umod:HI
	    (match_dup 1)
	    (zero_extend:HI (match_dup 2)))))]
  "TARGET_H8300H || TARGET_H8300S"
  "*
{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return \"divxu.b\\t%X2,%T0\";
  else
    return \"divxu.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
}"
  [(set_attr "length" "4")
   (set_attr "cc" "clobber")])

(define_insn "divmodqi4"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI
	  (div:HI
	    (match_operand:HI 1 "register_operand" "0")
	    (sign_extend:HI (match_operand:QI 2 "register_operand" "r")))))
   (set (match_operand:QI 3 "register_operand" "=r")
	(truncate:QI
	  (mod:HI
	    (match_dup 1)
	    (sign_extend:HI (match_dup 2)))))]
  "TARGET_H8300H || TARGET_H8300S"
  "*
{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return \"divxs.b\\t%X2,%T0\";
  else
    return \"divxs.b\\t%X2,%T0\;mov.b\\t%t0,%s3\";
}"
  [(set_attr "length" "6")
   (set_attr "cc" "clobber")])

(define_insn "udivmodhi4"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(truncate:HI
	  (udiv:SI
	    (match_operand:SI 1 "register_operand" "0")
	    (zero_extend:SI (match_operand:HI 2 "register_operand" "r")))))
   (set (match_operand:HI 3 "register_operand" "=r")
	(truncate:HI
	  (umod:SI
	    (match_dup 1)
	    (zero_extend:SI (match_dup 2)))))]
  "TARGET_H8300H || TARGET_H8300S"
  "*
{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return \"divxu.w\\t%T2,%S0\";
  else
    return \"divxu.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
}"
  [(set_attr "length" "4")
   (set_attr "cc" "clobber")])

(define_insn "divmodhi4"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(truncate:HI
	  (div:SI
	    (match_operand:SI 1 "register_operand" "0")
	    (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))))
   (set (match_operand:HI 3 "register_operand" "=r")
	(truncate:HI
	  (mod:SI
	    (match_dup 1)
	    (sign_extend:SI (match_dup 2)))))]
  "TARGET_H8300H || TARGET_H8300S"
  "*
{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return \"divxs.w\\t%T2,%S0\";
  else
    return \"divxs.w\\t%T2,%S0\;mov.w\\t%e0,%f3\";
}"
  [(set_attr "length" "6")
   (set_attr "cc" "clobber")])

;; ----------------------------------------------------------------------
;; AND INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn ""
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(and:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "nonmemory_operand" "rn,O")))]
  "register_operand (operands[0], QImode) || o_operand (operands[2], QImode)"
  "@
   and	%X2,%X0
   bclr	%W2,%R0"
  [(set_attr "length" "2,8")
   (set_attr "adjust_length" "no")
   (set_attr "cc" "set_znv,none_0hit")])

(define_expand "andqi3"
  [(set (match_operand:QI 0 "bit_operand" "")
	(and:QI (match_operand:QI 1 "bit_operand" "")
		(match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (fix_bit_operand (operands, 'O', AND))
    DONE;
}")

(define_expand "andhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(and:HI (match_operand:HI 1 "register_operand" "")
		(match_operand:HI 2 "nonmemory_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r")
	(and:HI (match_operand:HI 1 "register_operand" "%0")
		(match_operand:HI 2 "nonmemory_operand" "rn")))]
  "TARGET_H8300"
  "* return output_logical_op (HImode, AND, operands);"
  [(set_attr "length" "4")
   (set_attr "cc" "clobber")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(and:HI (match_operand:HI 1 "register_operand" "%0,0")
		(match_operand:HI 2 "nonmemory_operand" "r,n")))]
  "TARGET_H8300H || TARGET_H8300S"
  "* return output_logical_op (HImode, AND, operands);"
  [(set_attr "length" "2,4")
   (set_attr "cc" "set_znv,clobber")])

(define_insn "*andorhi3"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ior:HI (and:HI (match_operand:HI 2 "register_operand" "r")
			(match_operand:HI 3 "const_int_operand" "n"))
	(match_operand:HI 1 "register_operand" "0")))]
  "exact_log2 (INTVAL (operands[3]) & 0xffff) != -1"
  "*
{
  operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
  if (INTVAL (operands[3]) > 128)
    {
      operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
      return \"bld\\t%V3,%t2\;bst\\t%V3,%t0\";
    }
  return \"bld\\t%V3,%s2\;bst\\t%V3,%s0\";
}"
  [(set_attr "length" "4")
   (set_attr "cc" "clobber")])

(define_expand "andsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(and:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operand:SI 1 "register_operand" "%0")
		(match_operand:SI 2 "nonmemory_operand" "rn")))]
  "TARGET_H8300"
  "* return output_logical_op (SImode, AND, operands);"
  [(set_attr "length" "8")
   (set_attr "cc" "clobber")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "r,n")))]
  "TARGET_H8300H || TARGET_H8300S"
  "* return output_logical_op (SImode, AND, operands);"
  [(set_attr "length" "4,6")
   (set_attr "cc" "set_znv,clobber")])

;; ----------------------------------------------------------------------
;; OR INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn ""
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(ior:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "nonmemory_operand" "rn,n")))]
  "register_operand (operands[0], QImode)
   || (GET_CODE (operands[2]) == CONST_INT
       && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"or\t%X2,%X0\";
    case 1:
      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
      return \"bset\t%V2,%R0\";
    default:
      abort ();
    }
}"
  [(set_attr "length" "2,8")
   (set_attr "adjust_length" "no")
   (set_attr "cc" "set_znv,none_0hit")])

(define_expand "iorqi3"
  [(set (match_operand:QI 0 "bit_operand" "")
	(ior:QI (match_operand:QI 1 "bit_operand" "")
		(match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (fix_bit_operand (operands, 'P', IOR))
    DONE;
}")

(define_expand "iorhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(ior:HI (match_operand:HI 1 "register_operand" "")
		(match_operand:HI 2 "nonmemory_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=r,r")
	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
		(match_operand:HI 2 "general_operand" "J,rn")))]
  "TARGET_H8300"
  "* return output_logical_op (HImode, IOR, operands);"
  [(set_attr "length" "2,4")
   (set_attr "cc" "clobber,clobber")])

(define_insn ""
  [(set (match_operand:HI 0 "general_operand" "=r,r,r")
	(ior:HI (match_operand:HI 1 "general_operand" "%0,0,0")
		(match_operand:HI 2 "general_operand" "J,r,n")))]
  "TARGET_H8300H || TARGET_H8300S"
  "* return output_logical_op (HImode, IOR, operands);"
  [(set_attr "length" "2,2,4")
   (set_attr "cc" "clobber,set_znv,clobber")])

(define_expand "iorsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(ior:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
  "TARGET_H8300"
  "* return output_logical_op (SImode, IOR, operands);"
  [(set_attr "length" "2,8")
   (set_attr "cc" "clobber,clobber")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
	(ior:SI (match_operand:SI 1 "register_operand" "%0,0,0")
		(match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
  "TARGET_H8300H || TARGET_H8300S"
  "* return output_logical_op (SImode, IOR, operands);"
  [(set_attr "length" "2,4,6")
   (set_attr "cc" "clobber,set_znv,clobber")])

;; ----------------------------------------------------------------------
;; XOR INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn ""
  [(set (match_operand:QI 0 "bit_operand" "=r,U")
	(xor:QI (match_operand:QI 1 "bit_operand" "%0,0")
		(match_operand:QI 2 "nonmemory_operand" "rn,n")))]
  "register_operand (operands[0], QImode)
   || (GET_CODE (operands[2]) == CONST_INT
       && exact_log2 (INTVAL (operands[2]) & 0xff) != -1)"
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"xor\t%X2,%X0\";
    case 1:
      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
      return \"bnot\t%V2,%R0\";
    default:
      abort ();
    }
}"
  [(set_attr "length" "2,8")
   (set_attr "adjust_length" "no")
   (set_attr "cc" "set_znv,none_0hit")])

(define_expand "xorqi3"
  [(set (match_operand:QI 0 "bit_operand" "")
	(xor:QI (match_operand:QI 1 "bit_operand" "")
		(match_operand:QI 2 "nonmemory_operand" "")))]
  ""
  "
{
  if (fix_bit_operand (operands, 'O', XOR))
    DONE;
}")

(define_expand "xorhi3"
  [(set (match_operand:HI 0 "register_operand" "")
	(xor:HI (match_operand:HI 1 "register_operand" "")
		(match_operand:HI 2 "nonmemory_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r,r")
	(xor:HI (match_operand:HI 1 "register_operand" "%0,0")
		(match_operand:HI 2 "nonmemory_operand" "J,rn")))]
  "TARGET_H8300"
  "* return output_logical_op (HImode, XOR, operands);"
  [(set_attr "length" "2,4")
   (set_attr "cc" "clobber,clobber")])

(define_insn ""
  [(set (match_operand:HI 0 "register_operand" "=r,r,r")
	(xor:HI (match_operand:HI 1 "register_operand" "%0,0,0")
		(match_operand:HI 2 "nonmemory_operand" "J,r,n")))]
  "TARGET_H8300H || TARGET_H8300S"
  "* return output_logical_op (HImode, XOR, operands);"
  [(set_attr "length" "2,2,4")
   (set_attr "cc" "clobber,set_znv,clobber")])

(define_expand "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "")
	(xor:SI (match_operand:SI 1 "register_operand" "")
		(match_operand:SI 2 "nonmemory_operand" "")))]
  ""
  "")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
		(match_operand:SI 2 "nonmemory_operand" "J,rn")))]
  "TARGET_H8300"
  "* return output_logical_op (SImode, XOR, operands);"
  [(set_attr "length" "2,8")
   (set_attr "cc" "clobber,clobber")])

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r,r")
	(xor:SI (match_operand:SI 1 "register_operand" "%0,0,0")
		(match_operand:SI 2 "nonmemory_operand" "J,r,n")))]
  "TARGET_H8300H || TARGET_H8300S"
  "* return output_logical_op (SImode, XOR, operands);"
  [(set_attr "length" "2,4,6")
   (set_attr "cc" "clobber,set_znv,clobber")])

;; ----------------------------------------------------------------------
;; NEGATION INSTRUCTIONS
;; ----------------------------------------------------------------------

(define_insn "negqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(neg:QI (match_operand:QI 1 "register_operand" "0")))]
  ""
  "neg	%X0"
  [(set_attr "length" "2")
   (set_attr "cc" "set_zn")])

(define_expand "neghi2"
  [(set (match_operand:HI 0 "register_operand" "")
	(neg:HI (match_operand:HI 1 "register_operand" "")))]
  ""
  "
{
  if (TARGET_H8300)
    {
      emit_insn (gen_neghi2_h8300 (operands[0], operands[1]));
      DONE;
    }
}")

(define_expand "neghi2_h8300"
  [(set (match_dup 2)
	(not:HI (match_operand:HI 1 "register_operand" "")))
   (set (match_dup 2) (plus:HI (match_dup 2) (const_int 1)))
   (set (match_operand:HI 0 "register_operand" "")
	(match_dup 2))]
  ""
  "operands[2] = gen_reg_rtx (HImode);")

(define_insn "neghi2_h8300h"
  [(set (match_operand:HI 0 "register_operand" "=r")