convex.h

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#else

#define CPP_SPEC							\
"%{mc1:-D__convex_c1__}							\
 %{mc2:-D__convex_c2__}							\
 %{mc32:-D__convex_c32__}						\
 %{mc34:-D__convex_c34__}						\
 %{fno-builtin:-D__NO_INLINE}						\
 -D__NO_INLINE_MATH -D__NO_INLINE_STDLIB				\
 -D_CONVEX_FLOAT_							\
 %{!mc1:%{!mc2:%{!mc32:%{!mc34:-D__convex_c38__}}}}			\
 %{.S:-P}								\
 %{!traditional:-D__stdc__}						\
 %{!traditional:-D_LONGLONG}						\
 %{!traditional:-Ds64_t=long\\ long -Du64_t=unsigned\\ long\\ long}	\
 %{!ansi:-D_POSIX_SOURCE}						\
 %{!ansi:-D_CONVEX_SOURCE}"

#endif

#define LIB_SPEC							\
"%{mc1:-lC1%{traditional:_old}%{p:_p}%{pg:_p}}				\
 %{mc2:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
 %{mc32:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
 %{mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}				\
 %{!mc1:%{!mc2:%{!mc32:%{!mc34:-lC2%{traditional:_old}%{p:_p}%{pg:_p}}}}} \
 -lc%{traditional:_old}%{p:_p}%{pg:_p}"

#endif

#if _IEEE_FLOAT_

/* ieee default */

#define ASM_SPEC "-fi"

#define LINK_SPEC							\
"-E%{traditional:no}posix						\
 -X									\
 %{F} %{M*} %{y*}							\
 -fi									\
 -A__iob=___ap$iob							\
 -A_use_libc_sema=___ap$use_libc_sema					\
 %{traditional:-A___gcc_cleanup=__cleanup}				\
 %{!traditional:-A___gcc_cleanup=___ap$do_registered_functions}		\
 -L/usr/lib"

#define STARTFILE_SPEC							\
"%{!pg:%{!p:/usr/lib/crt/crt0.o}}					\
 %{!pg:%{p:/usr/lib/crt/mcrt0.o}}					\
 %{pg:/usr/lib/crt/gcrt0.o}						\
 /usr/lib/crt/fpmode_i.o"

#else

/* native default */

#define ASM_SPEC "-fn"

#define LINK_SPEC							\
"-E%{traditional:no}posix						\
 -X									\
 %{F} %{M*} %{y*}							\
 -fn									\
 -A__iob=___ap$iob							\
 -A_use_libc_sema=___ap$use_libc_sema					\
 %{traditional:-A___gcc_cleanup=__cleanup}				\
 %{!traditional:-A___gcc_cleanup=___ap$do_registered_functions}		\
 -L/usr/lib"

#define STARTFILE_SPEC							\
"%{!pg:%{!p:/usr/lib/crt/crt0.o}}					\
 %{!pg:%{p:/usr/lib/crt/mcrt0.o}}					\
 %{pg:/usr/lib/crt/gcrt0.o}"

#endif

/* Use /path/libgcc.a instead of -lgcc, makes bootstrap work more smoothly.  */

#define LINK_LIBGCC_SPECIAL_1

/* Since IEEE support was added to gcc, most things seem to like it
   better if we disable exceptions and check afterward for infinity.  */

#if __convex__
#if _IEEE_FLOAT_
#define REAL_VALUE_ISNAN(x) 0
#define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0x7ff0) == 0x7ff0)
#else
#define REAL_VALUE_ISNAN(x) 0
#define REAL_VALUE_ISINF(x) ((*(short *) &(x) & 0xfff0) == 0x8000)
#endif
#endif

/* Target machine storage layout */

/* Define this if most significant bit is lowest numbered
   in instructions that operate on numbered bit-fields.  */
#define BITS_BIG_ENDIAN 1

/* Define this if most significant byte of a word is the lowest numbered.  */
#define BYTES_BIG_ENDIAN 1

/* Define this if most significant word of a multiword number is numbered.  */
#define WORDS_BIG_ENDIAN 1

/* Number of bits in an addressable storage unit */
#define BITS_PER_UNIT 8

/* Width in bits of a "word", which is the contents of a machine register.
   Note that this is not necessarily the width of data type `int';
   if using 16-bit ints on a 68000, this would still be 32.
   But on a machine with 16-bit registers, this would be 16.  */
#define BITS_PER_WORD 64

/* Width of a word, in units (bytes).  */
#define UNITS_PER_WORD 8

/* Width in bits of a pointer.
   See also the macro `Pmode' defined below.  */
#define POINTER_SIZE 32

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */
#define PARM_BOUNDARY 32

/* Boundary (in *bits*) on which stack pointer should be aligned.  */
#define STACK_BOUNDARY 64

/* Allocation boundary (in *bits*) for the code of a function.  */
#define FUNCTION_BOUNDARY 16

/* Alignment of field after `int : 0' in a structure.  */
#define EMPTY_FIELD_BOUNDARY 32

/* Every structure's size must be a multiple of this.  */
#define STRUCTURE_SIZE_BOUNDARY 8

/* A bitfield declared as `int' forces `int' alignment for the struct.  */
#define PCC_BITFIELD_TYPE_MATTERS 1

/* No data type wants to be aligned rounder than this.  */
/* beware of doubles in structs -- 64 is incompatible with cc */
#define BIGGEST_ALIGNMENT 32

/* Set this nonzero if move instructions will actually fail to work
   when given unaligned data.  */
#define STRICT_ALIGNMENT 0

/* Define sizes of basic C types to conform to ordinary usage -- these
   types depend on BITS_PER_WORD otherwise.  */
#define CHAR_TYPE_SIZE		8
#define SHORT_TYPE_SIZE		16
#define INT_TYPE_SIZE		32
#define LONG_TYPE_SIZE		(TARGET_LONG64 ? 64 : 32)
#define LONG_LONG_TYPE_SIZE	64
#define FLOAT_TYPE_SIZE		32
#define DOUBLE_TYPE_SIZE	64
#define LONG_DOUBLE_TYPE_SIZE	64
#define MAX_LONG_TYPE_SIZE      64

/* Declare the standard types used by builtins to match convex stddef.h --
   with int rather than long.  */

#define SIZE_TYPE "unsigned int"
#define PTRDIFF_TYPE "int"

/* Standard register usage.  */

/* Number of actual hardware registers.
   The hardware registers are assigned numbers for the compiler
   from 0 to just below FIRST_PSEUDO_REGISTER.
   All registers that the compiler knows about must be given numbers,
   even those that are not normally considered general registers.  */
#define FIRST_PSEUDO_REGISTER 16

/* 1 for registers that have pervasive standard uses
   and are not available for the register allocator.
   For Convex, these are AP, FP, and SP.  */
#define FIXED_REGISTERS \
  { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1 }

/* 1 for registers not available across function calls.
   These must include the FIXED_REGISTERS and also any
   registers that can be used without being saved.
   The latter must include the registers where values are returned
   and the register where structure-value addresses are passed.
   Aside from that, you can include as many other registers as you like.  */
#define CALL_USED_REGISTERS \
  { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }

/* List the order in which to allocate registers.  Each register must be
   listed once, even those in FIXED_REGISTERS.
   For Convex, put S0 (the return register) last.  */
#define REG_ALLOC_ORDER \
  { 1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 0, 8, 14, 15 }

/* Return number of consecutive hard regs needed starting at reg REGNO
   to hold something of mode MODE.
   This is ordinarily the length in words of a value of mode MODE
   but can be less for certain modes in special long registers.  */
#define HARD_REGNO_NREGS(REGNO, MODE) \
   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
   On Convex, S registers can hold any type, A registers any nonfloat.  */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
  (S_REGNO_P (REGNO)							\
   || (GET_MODE_SIZE (MODE) <= 4 && (MODE) != SFmode))

/* Value is 1 if it is a good idea to tie two pseudo registers
   when one has mode MODE1 and one has mode MODE2.
   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
   for any hard reg, then this must be 0 for correct output.  */
#define MODES_TIEABLE_P(MODE1, MODE2)  \
  ((GET_MODE_SIZE (MODE1) <= 4 && (MODE1) != SFmode)			\
   == (GET_MODE_SIZE (MODE2) <= 4 && (MODE2) != SFmode))

/* Specify the registers used for certain standard purposes.
   The values of these macros are register numbers.  */

#define S0_REGNUM 0
#define A0_REGNUM 8

/* Register to use for pushing function arguments.  */
#define STACK_POINTER_REGNUM A0_REGNUM

/* Base register for access to local variables of the function.  */
#define FRAME_POINTER_REGNUM (A0_REGNUM + 7)

/* Value should be nonzero if functions must have frame pointers.
   Zero means the frame pointer need not be set up (and parms
   may be accessed via the stack pointer) in functions that seem suitable.
   This is computed in `reload', in reload1.c.  */
#define FRAME_POINTER_REQUIRED 1

/* Base register for access to arguments of the function.  */
#define ARG_POINTER_REGNUM (A0_REGNUM + 6)

/* Register in which static-chain is passed to a function.
   Use S0, not an A reg, because this rare use would otherwise prevent
   an A reg from being available to global-alloc across calls.  */
#define STATIC_CHAIN_REGNUM S0_REGNUM

/* Register in which address to store a structure value
   is passed to a function.  */
#define STRUCT_VALUE_REGNUM (A0_REGNUM + 1)

/* Define the classes of registers for register constraints in the
   machine description.  Also define ranges of constants.

   One of the classes must always be named ALL_REGS and include all hard regs.
   If there is more than one class, another class must be named NO_REGS
   and contain no registers.

   The name GENERAL_REGS must be the name of a class (or an alias for
   another name such as ALL_REGS).  This is the class of registers
   that is allowed by "g" or "r" in a register constraint.
   Also, registers outside this class are allocated only when
   instructions express preferences for them.

   The classes must be numbered in nondecreasing order; that is,
   a larger-numbered class must never be contained completely
   in a smaller-numbered class.

   For any two classes, it is very desirable that there be another
   class that represents their union.  */
   
/* Convex has classes A (address) and S (scalar).
   A is further divided into SP_REGS (stack pointer) and INDEX_REGS.
   SI_REGS is S_REGS + INDEX_REGS -- all the regs except SP.  */

enum reg_class {
  NO_REGS, S_REGS, INDEX_REGS, SP_REGS, A_REGS, SI_REGS,
  ALL_REGS, LIM_REG_CLASSES 
};

#define N_REG_CLASSES (int) LIM_REG_CLASSES

/* Since GENERAL_REGS is the same class as ALL_REGS,
   don't give it a different class number; just make it an alias.  */

#define GENERAL_REGS ALL_REGS

/* Give names of register classes as strings for dump file.   */

#define REG_CLASS_NAMES \
 {"NO_REGS", "S_REGS", "INDEX_REGS", "SP_REGS", "A_REGS", "SI_REGS", \
  "ALL_REGS" }

/* Define which registers fit in which classes.
   This is an initializer for a vector of HARD_REG_SET
   of length N_REG_CLASSES.  */

#define REG_CLASS_CONTENTS \
  { {0}, {0x00ff}, {0xfe00}, {0x0100}, {0xff00}, {0xfeff}, {0xffff} }

/* The same information, inverted:
   Return the class number of the smallest class containing
   reg number REGNO.  This could be a conditional expression
   or could index an array.  */

#define REGNO_REG_CLASS(REGNO) (regno_reg_class[REGNO])

#define S_REGNO_P(REGNO) ((unsigned)((REGNO) - S0_REGNUM) < 8)
#define A_REGNO_P(REGNO) ((unsigned)((REGNO) - A0_REGNUM) < 8)

#define S_REG_P(X) (REG_P (X) && S_REGNO_P (REGNO (X)))
#define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))

/* The class value for index registers, and the one for base regs.  */

#define INDEX_REG_CLASS INDEX_REGS
#define BASE_REG_CLASS INDEX_REGS

/* Get reg_class from a letter such as appears in the machine description.  */
/* a => A_REGS
   d => S_REGS  ('s' is taken)
   A => INDEX_REGS  (i.e., A_REGS except sp) */

#define REG_CLASS_FROM_LETTER(C) \
  reg_class_from_letter[(unsigned char) (C)]

/* The letters I, J, K, L and M in a register constraint string
   can be used to stand for particular ranges of immediate operands.
   This macro defines what the ranges are.
   C is the letter, and VALUE is a constant value.
   Return 1 if VALUE is in the range specified by C.  */
/* 'I' is used to pass any CONST_INT and reject any CONST_DOUBLE.
   CONST_DOUBLE integers are handled by G and H constraint chars.  */

#define CONST_OK_FOR_LETTER_P(VALUE, C)  1

/* Similar, but for floating constants, and defining letters G and H.
   Here VALUE is the CONST_DOUBLE rtx itself.  */
/* Convex uses G, H:
   value usable in ld.d (low word 0) or ld.l (high word all sign) */

#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C)				\
  (((C) == 'G' && LD_D_P (VALUE)) ||					\
   ((C) == 'H' && LD_L_P (VALUE)) ||					\
   0)