pa.h

gcc3.2.1源代码

	fputs ("\t.dword 0\n", FILE);					\
	fputs ("\tmfia	%r31\n", FILE);					\
	fputs ("\tldd	24(%r31),%r1\n", FILE);				\
	fputs ("\tldd	24(%r1),%r27\n", FILE);				\
	fputs ("\tldd	16(%r1),%r1\n", FILE);				\
	fputs ("\tbve	(%r1)\n", FILE);				\
	fputs ("\tldd	32(%r31),%r31\n", FILE);			\
	fputs ("\t.dword 0  ; fptr\n", FILE);				\
	fputs ("\t.dword 0  ; static link\n", FILE);			\
      }									\
  }

/* Length in units of the trampoline for entering a nested function.

   Flush the cache entries corresponding to the first and last addresses
   of the trampoline.  This is necessary as the trampoline may cross two
   cache lines.

   If the code part of the trampoline ever grows to > 32 bytes, then it
   will become necessary to hack on the cacheflush pattern in pa.md.  */

#define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)

/* Emit RTL insns to initialize the variable parts of a trampoline.
   FNADDR is an RTX for the address of the function's pure code.
   CXT is an RTX for the static chain value for the function.

   Move the function address to the trampoline template at offset 36.
   Move the static chain value to trampoline template at offset 40.
   Move the trampoline address to trampoline template at offset 44.
   Move r19 to trampoline template at offset 48.  The latter two
   words create a plabel for the indirect call to the trampoline.  */

#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) 			\
{									\
  if (! TARGET_64BIT)							\
    {									\
      rtx start_addr, end_addr;						\
									\
      start_addr = memory_address (Pmode, plus_constant ((TRAMP), 36));	\
      emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (FNADDR));	\
      start_addr = memory_address (Pmode, plus_constant ((TRAMP), 40));	\
      emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (CXT));		\
      start_addr = memory_address (Pmode, plus_constant ((TRAMP), 44));	\
      emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (TRAMP));	\
      start_addr = memory_address (Pmode, plus_constant ((TRAMP), 48));	\
      emit_move_insn (gen_rtx_MEM (Pmode, start_addr),			\
		      gen_rtx_REG (Pmode, 19));				\
      /* fdc and fic only use registers for the address to flush,	\
	 they do not accept integer displacements.  */ 			\
      start_addr = force_reg (Pmode, (TRAMP));				\
      end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32));	\
      emit_insn (gen_dcacheflush (start_addr, end_addr));		\
      end_addr = force_reg (Pmode, plus_constant (start_addr, 32));	\
      emit_insn (gen_icacheflush (start_addr, end_addr, start_addr,	\
				  gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\
    }									\
  else									\
    {									\
      rtx start_addr, end_addr;						\
									\
      start_addr = memory_address (Pmode, plus_constant ((TRAMP), 56));	\
      emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (FNADDR));	\
      start_addr = memory_address (Pmode, plus_constant ((TRAMP), 64));	\
      emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (CXT));		\
      /* Create a fat pointer for the trampoline.  */			\
      end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32));	\
      start_addr = memory_address (Pmode, plus_constant ((TRAMP), 16));	\
      emit_move_insn (gen_rtx_MEM (Pmode, start_addr), end_addr);	\
      end_addr = gen_rtx_REG (Pmode, 27);				\
      start_addr = memory_address (Pmode, plus_constant ((TRAMP), 24));	\
      emit_move_insn (gen_rtx_MEM (Pmode, start_addr), end_addr);	\
      /* fdc and fic only use registers for the address to flush,	\
	 they do not accept integer displacements.  */ 			\
      start_addr = force_reg (Pmode, (TRAMP));				\
      end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32));	\
      emit_insn (gen_dcacheflush (start_addr, end_addr));		\
      end_addr = force_reg (Pmode, plus_constant (start_addr, 32));	\
      emit_insn (gen_icacheflush (start_addr, end_addr, start_addr,	\
				  gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\
    }									\
}

/* Perform any machine-specific adjustment in the address of the trampoline.
   ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
   Adjust the trampoline address to point to the plabel at offset 44.  */
   
#define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
  if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))

/* Emit code for a call to builtin_saveregs.  We must emit USE insns which
   reference the 4 integer arg registers and 4 fp arg registers.
   Ordinarily they are not call used registers, but they are for
   _builtin_saveregs, so we must make this explicit.  */

#define EXPAND_BUILTIN_SAVEREGS() hppa_builtin_saveregs ()

/* Implement `va_start' for varargs and stdarg.  */

#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
  hppa_va_start (stdarg, valist, nextarg)

/* Implement `va_arg'.  */

#define EXPAND_BUILTIN_VA_ARG(valist, type) \
  hppa_va_arg (valist, type)

/* Addressing modes, and classification of registers for them. 

   Using autoincrement addressing modes on PA8000 class machines is
   not profitable.  */

#define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
#define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)

#define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
#define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)

/* Macros to check register numbers against specific register classes.  */

/* These assume that REGNO is a hard or pseudo reg number.
   They give nonzero only if REGNO is a hard reg of the suitable class
   or a pseudo reg currently allocated to a suitable hard reg.
   Since they use reg_renumber, they are safe only once reg_renumber
   has been allocated, which happens in local-alloc.c.  */

#define REGNO_OK_FOR_INDEX_P(REGNO) \
  ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
#define REGNO_OK_FOR_BASE_P(REGNO)  \
  ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
#define REGNO_OK_FOR_FP_P(REGNO) \
  (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO]))

/* Now macros that check whether X is a register and also,
   strictly, whether it is in a specified class.

   These macros are specific to the HP-PA, and may be used only
   in code for printing assembler insns and in conditions for
   define_optimization.  */

/* 1 if X is an fp register.  */

#define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))

/* Maximum number of registers that can appear in a valid memory address.  */

#define MAX_REGS_PER_ADDRESS 2

/* Recognize any constant value that is a valid address except
   for symbolic addresses.  We get better CSE by rejecting them
   here and allowing hppa_legitimize_address to break them up.  We
   use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE.  */

#define CONSTANT_ADDRESS_P(X) \
  ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF		\
   || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST		\
   || GET_CODE (X) == HIGH) 						\
   && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))

/* Include all constant integers and constant doubles, but not
   floating-point, except for floating-point zero.

   Reject LABEL_REFs if we're not using gas or the new HP assembler. 

   ?!? For now also reject CONST_DOUBLES in 64bit mode.  This will need
   further work.  */
#ifndef NEW_HP_ASSEMBLER
#define NEW_HP_ASSEMBLER 0
#endif
#define LEGITIMATE_CONSTANT_P(X)				\
  ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT			\
    || (X) == CONST0_RTX (GET_MODE (X)))			\
   && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF)	\
   && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE)		\
   && !(TARGET_64BIT && GET_CODE (X) == CONST_INT		\
	&& !(HOST_BITS_PER_WIDE_INT <= 32			\
	     || (INTVAL (X) >= (HOST_WIDE_INT) -32 << 31	\
		 && INTVAL (X) < (HOST_WIDE_INT) 32 << 31)	\
	     || cint_ok_for_move (INTVAL (X))))			\
   && !function_label_operand (X, VOIDmode))

/* Subroutine for EXTRA_CONSTRAINT.

   Return 1 iff OP is a pseudo which did not get a hard register and
   we are running the reload pass.  */

#define IS_RELOADING_PSEUDO_P(OP) \
  ((reload_in_progress					\
    && GET_CODE (OP) == REG				\
    && REGNO (OP) >= FIRST_PSEUDO_REGISTER		\
    && reg_renumber [REGNO (OP)] < 0))

/* Optional extra constraints for this machine. Borrowed from sparc.h.

   For the HPPA, `Q' means that this is a memory operand but not a
   symbolic memory operand.  Note that an unassigned pseudo register
   is such a memory operand.  Needed because reload will generate
   these things in insns and then not re-recognize the insns, causing
   constrain_operands to fail.

   `R' is used for scaled indexed addresses.

   `S' is the constant 31.

   `T' is for fp loads and stores.  */
#define EXTRA_CONSTRAINT(OP, C)				\
  ((C) == 'Q' ?						\
   (IS_RELOADING_PSEUDO_P (OP)				\
    || (GET_CODE (OP) == MEM				\
	&& (memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
	    || reload_in_progress)			\
	&& ! symbolic_memory_operand (OP, VOIDmode)	\
        && !(GET_CODE (XEXP (OP, 0)) == PLUS		\
	     && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
		 || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT))))\
   : ((C) == 'R' ?					\
     (GET_CODE (OP) == MEM				\
      && GET_CODE (XEXP (OP, 0)) == PLUS		\
      && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT	\
	  || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT)	\
      && (move_operand (OP, GET_MODE (OP))		\
	  || memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
	  || reload_in_progress))			\
   : ((C) == 'T' ? 					\
      (GET_CODE (OP) == MEM				\
       /* Using DFmode forces only short displacements	\
	  to be recognized as valid in reg+d addresses. \
	  However, this is not necessary for PA2.0 since\
	  it has long FP loads/stores.  */		\
       && memory_address_p ((TARGET_PA_20		\
			     ? GET_MODE (OP)		\
			     : DFmode),			\
			    XEXP (OP, 0))		\
       && !(GET_CODE (XEXP (OP, 0)) == LO_SUM		\
	    && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
	    && REG_OK_FOR_BASE_P (XEXP (XEXP (OP, 0), 0))\
	    && GET_CODE (XEXP (XEXP (OP, 0), 1)) == UNSPEC\
	    && GET_MODE (XEXP (OP, 0)) == Pmode)	\
       && !(GET_CODE (XEXP (OP, 0)) == PLUS		\
	    && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
		|| GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT)))\
   : ((C) == 'U' ?					\
      (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63)	\
   : ((C) == 'A' ?					\
      (GET_CODE (OP) == MEM				\
       && GET_CODE (XEXP (OP, 0)) == LO_SUM		\
       && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG	\
       && REG_OK_FOR_BASE_P (XEXP (XEXP (OP, 0), 0))	\
       && GET_CODE (XEXP (XEXP (OP, 0), 1)) == UNSPEC		\
       && GET_MODE (XEXP (OP, 0)) == Pmode)			\
   : ((C) == 'S' ?					\
      (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) : 0))))))
	

/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
   and check its validity for a certain class.
   We have two alternate definitions for each of them.
   The usual definition accepts all pseudo regs; the other rejects
   them unless they have been allocated suitable hard regs.
   The symbol REG_OK_STRICT causes the latter definition to be used.

   Most source files want to accept pseudo regs in the hope that
   they will get allocated to the class that the insn wants them to be in.
   Source files for reload pass need to be strict.
   After reload, it makes no difference, since pseudo regs have
   been eliminated by then.  */

#ifndef REG_OK_STRICT

/* Nonzero if X is a hard reg that can be used as an index
   or if it is a pseudo reg.  */
#define REG_OK_FOR_INDEX_P(X) \
(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
/* Nonzero if X is a hard reg that can be used as a base reg
   or if it is a pseudo reg.  */
#define REG_OK_FOR_BASE_P(X) \
(REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))

#else

/* Nonzero if X is a hard reg that can be used as an index.  */
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as a base reg.  */
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))

#endif

/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
   that is a valid memory address for an instruction.
   The MODE argument is the machine mode for the MEM expression
   that wants to use this address.

   On the HP-PA, the actual legitimate addresses must be
   REG+REG, REG+(REG*SCALE) or REG+SMALLINT.
   But we can treat a SYMBOL_REF as legitimate if it is part of this
   function's constant-pool, because such addresses can actually
   be output as REG+SMALLINT. 

   Note we only allow 5 bit immediates for access to a constant address;
   doing so avoids losing for loading/storing a FP register at an address
   which will not fit in 5 bits.  */

#define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
#define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))

#define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
#define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))

#define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
#define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))

#define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
#define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))

#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR)  \
{							\
  if ((REG_P (X) && REG_OK_FOR_BASE_P (X))		\
      || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC		\
	   || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC)	\
	  && REG_P (XEXP (X, 0))			\
	  && REG_OK_FOR_BASE_P (XEXP (X, 0))))		\
    goto ADDR;						\
  else if (GET_CODE (X) == PLUS)			\
    {							\
      rtx base = 0, index = 0;				\
      if (REG_P (XEXP (X, 0))				\
	  && REG_OK_FOR_BASE_P (XEXP (X, 0)))		\
	base = XEXP (X, 0), index = XEXP (X, 1);	\
      else if (REG_P (XEXP (X, 1))			\
	       && REG_OK_FOR_BASE_P (XEXP (X, 1)))	\
	base = XEXP (X, 1), index = XEXP (X, 0);	\
      if (base != 0)					\
	if (GET_CODE (index) == CONST_INT		\
	    && ((INT_14_BITS (index)			\
		 && (TARGET_SOFT_FLOAT			\
		     || (TARGET_PA_20		\