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"" "* return out_tstsi (insn,NULL);" [(set_attr "cc" "compare") (set_attr "length" "4")])(define_insn "*negated_tstsi" [(set (cc0) (neg:SI (match_operand:SI 0 "register_operand" "r")))] "" "cp __zero_reg__,%A0 cpc __zero_reg__,%B0 cpc __zero_reg__,%C0 cpc __zero_reg__,%D0" [(set_attr "cc" "compare") (set_attr "length" "4")])(define_insn "cmpqi" [(set (cc0) (compare (match_operand:QI 0 "register_operand" "r,d") (match_operand:QI 1 "nonmemory_operand" "r,i")))] "" "@ cp %0,%1 cpi %0,lo8(%1)" [(set_attr "cc" "compare,compare") (set_attr "length" "1,1")])(define_insn "*cmpqi_sign_extend" [(set (cc0) (compare (sign_extend:HI (match_operand:QI 0 "register_operand" "d")) (match_operand:HI 1 "immediate_operand" "M")))] "" "cpi %0,lo8(%1)" [(set_attr "cc" "compare") (set_attr "length" "1")])(define_insn "cmphi" [(set (cc0) (compare (match_operand:HI 0 "register_operand" "r,d,d,r,r") (match_operand:HI 1 "nonmemory_operand" "r,M,i,M,i"))) (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))] "" "*{ switch (which_alternative) { case 0: return (AS2 (cp,%A0,%A1) CR_TAB AS2 (cpc,%B0,%B1)); case 1: if (reg_unused_after (insn, operands[0]) && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63 && test_hard_reg_class (ADDW_REGS, operands[0])) return AS2 (sbiw,%0,%1); else return (AS2 (cpi,%0,%1) CR_TAB AS2 (cpc,%B0,__zero_reg__)); case 2: if (reg_unused_after (insn, operands[0])) return (AS2 (subi,%0,lo8(%1)) CR_TAB AS2 (sbci,%B0,hi8(%1))); else return (AS2 (ldi, %2,hi8(%1)) CR_TAB AS2 (cpi, %A0,lo8(%1)) CR_TAB AS2 (cpc, %B0,%2)); case 3: return (AS2 (ldi, %2,lo8(%1)) CR_TAB AS2 (cp, %A0,%2) CR_TAB AS2 (cpc, %B0,__zero_reg__)); case 4: return (AS2 (ldi, %2,lo8(%1)) CR_TAB AS2 (cp, %A0,%2) CR_TAB AS2 (ldi, %2,hi8(%1)) CR_TAB AS2 (cpc, %B0,%2)); } return \"bug\";}" [(set_attr "cc" "compare,compare,compare,compare,compare") (set_attr "length" "2,2,3,3,4")])(define_insn "cmpsi" [(set (cc0) (compare (match_operand:SI 0 "register_operand" "r,d,d,r,r") (match_operand:SI 1 "nonmemory_operand" "r,M,i,M,i"))) (clobber (match_scratch:QI 2 "=X,X,&d,&d,&d"))] "" "*{ switch (which_alternative) { case 0: return (AS2 (cp,%A0,%A1) CR_TAB AS2 (cpc,%B0,%B1) CR_TAB AS2 (cpc,%C0,%C1) CR_TAB AS2 (cpc,%D0,%D1)); case 1: if (reg_unused_after (insn, operands[0]) && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 63 && test_hard_reg_class (ADDW_REGS, operands[0])) return (AS2 (sbiw,%0,%1) CR_TAB AS2 (cpc,%C0,__zero_reg__) CR_TAB AS2 (cpc,%D0,__zero_reg__)); else return (AS2 (cpi,%A0,lo8(%1)) CR_TAB AS2 (cpc,%B0,__zero_reg__) CR_TAB AS2 (cpc,%C0,__zero_reg__) CR_TAB AS2 (cpc,%D0,__zero_reg__)); case 2: if (reg_unused_after (insn, operands[0])) return (AS2 (subi,%A0,lo8(%1)) CR_TAB AS2 (sbci,%B0,hi8(%1)) CR_TAB AS2 (sbci,%C0,hlo8(%1)) CR_TAB AS2 (sbci,%D0,hhi8(%1))); else return (AS2 (cpi, %A0,lo8(%1)) CR_TAB AS2 (ldi, %2,hi8(%1)) CR_TAB AS2 (cpc, %B0,%2) CR_TAB AS2 (ldi, %2,hlo8(%1)) CR_TAB AS2 (cpc, %C0,%2) CR_TAB AS2 (ldi, %2,hhi8(%1)) CR_TAB AS2 (cpc, %D0,%2)); case 3: return (AS2 (ldi,%2,lo8(%1)) CR_TAB AS2 (cp,%A0,%2) CR_TAB AS2 (cpc,%B0,__zero_reg__) CR_TAB AS2 (cpc,%C0,__zero_reg__) CR_TAB AS2 (cpc,%D0,__zero_reg__)); case 4: return (AS2 (ldi, %2,lo8(%1)) CR_TAB AS2 (cp, %A0,%2) CR_TAB AS2 (ldi, %2,hi8(%1)) CR_TAB AS2 (cpc, %B0,%2) CR_TAB AS2 (ldi, %2,hlo8(%1)) CR_TAB AS2 (cpc, %C0,%2) CR_TAB AS2 (ldi, %2,hhi8(%1)) CR_TAB AS2 (cpc, %D0,%2)); } return \"bug\";}" [(set_attr "cc" "compare,compare,compare,compare,compare") (set_attr "length" "4,4,7,5,8")]);; ----------------------------------------------------------------------;; JUMP INSTRUCTIONS;; ----------------------------------------------------------------------;; Conditional jump instructions(define_expand "beq" [(set (pc) (if_then_else (eq (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")(define_expand "bne" [(set (pc) (if_then_else (ne (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")(define_expand "bge" [(set (pc) (if_then_else (ge (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")(define_expand "bgeu" [(set (pc) (if_then_else (geu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")(define_expand "blt" [(set (pc) (if_then_else (lt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")(define_expand "bltu" [(set (pc) (if_then_else (ltu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")/**************************************************************** AVR not have following conditional jumps: LE,LEU,GT,GTU. Convert them all to proper jumps.*****************************************************************/(define_expand "ble" [(set (pc) (if_then_else (le (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")(define_expand "bleu" [(set (pc) (if_then_else (leu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")(define_expand "bgt" [(set (pc) (if_then_else (gt (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")(define_expand "bgtu" [(set (pc) (if_then_else (gtu (cc0) (const_int 0)) (label_ref (match_operand 0 "" "")) (pc)))] "" "")(define_insn "*sbrx_branch" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(zero_extract (match_operand:QI 1 "register_operand" "r") (const_int 1) (match_operand 2 "immediate_operand" "n")) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE)" "* { int comp = ((get_attr_length (insn) == 4) ? reverse_condition (GET_CODE (operands[0])) : GET_CODE (operands[0])); if (comp == EQ) output_asm_insn (AS2 (sbrs,%1,%2), operands); else output_asm_insn (AS2 (sbrc,%1,%2), operands); if (get_attr_length (insn) != 4) return AS1 (rjmp,%3); return (AS1 (rjmp,_PC_+4) CR_TAB AS1 (jmp,%3)); }" [(set (attr "length") (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046)) (le (minus (pc) (match_dup 3)) (const_int 2046))) (const_int 2) (if_then_else (eq_attr "mcu_mega" "no") (const_int 2) (const_int 4)))) (set_attr "cc" "clobber")])(define_insn "*sbrx_and_branchsi" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(and:SI (match_operand:SI 1 "register_operand" "r") (match_operand:SI 2 "immediate_operand" "n")) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE) && mask_one_bit_p(INTVAL (operands[2]))" "* { int comp = ((get_attr_length (insn) == 4) ? reverse_condition (GET_CODE (operands[0])) : GET_CODE (operands[0])); int bit = mask_one_bit_p(INTVAL (operands[2])) - 1; static char buf[] = \"sbrc %A1,0\"; buf[3] = (comp == EQ ? 's' : 'c'); buf[6] = bit / 8 + 'A'; buf[9] = bit % 8 + '0'; output_asm_insn (buf, operands); if (get_attr_length (insn) != 4) return AS1 (rjmp,%3); return (AS1 (rjmp,_PC_+4) CR_TAB AS1 (jmp,%3)); }" [(set (attr "length") (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046)) (le (minus (pc) (match_dup 3)) (const_int 2046))) (const_int 2) (if_then_else (eq_attr "mcu_mega" "no") (const_int 2) (const_int 4)))) (set_attr "cc" "clobber")])(define_insn "*sbrx_and_branchhi" [(set (pc) (if_then_else (match_operator 0 "comparison_operator" [(and:HI (match_operand:HI 1 "register_operand" "r") (match_operand:HI 2 "immediate_operand" "n")) (const_int 0)]) (label_ref (match_operand 3 "" "")) (pc)))] "(GET_CODE (operands[0]) == EQ || GET_CODE (operands[0]) == NE) && mask_one_bit_p(INTVAL (operands[2]))" "* { int comp = ((get_attr_length (insn) == 4) ? reverse_condition (GET_CODE (operands[0])) : GET_CODE (operands[0])); int bit = mask_one_bit_p(INTVAL (operands[2])) - 1; static char buf[] = \"sbrc %A1,0\"; buf[3] = (comp == EQ ? 's' : 'c'); buf[6] = bit / 8 + 'A'; buf[9] = bit % 8 + '0'; output_asm_insn (buf, operands); if (get_attr_length (insn) != 4) return AS1 (rjmp,%3); return (AS1 (rjmp,_PC_+4) CR_TAB AS1 (jmp,%3)); }" [(set (attr "length") (if_then_else (and (ge (minus (pc) (match_dup 3)) (const_int -2046)) (le (minus (pc) (match_dup 3)) (const_int 2046))) (const_int 2) (if_then_else (eq_attr "mcu_mega" "no") (const_int 2) (const_int 4)))) (set_attr "cc" "clobber")]);; ************************************************************************;; Implementation of conditional jumps here.;; Compare with 0 (test) jumps;; ************************************************************************(define_insn "branch" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(cc0) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "! (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)" "* return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);" [(set_attr "type" "branch") (set_attr "cc" "clobber")])(define_insn "difficult_branch" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(cc0) (const_int 0)]) (label_ref (match_operand 0 "" "")) (pc)))] "(GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)" "* return ret_cond_branch (operands[1], avr_jump_mode (operands[0],insn), 0);" [(set_attr "type" "branch1") (set_attr "cc" "clobber")]);; revers branch(define_insn "rvbranch" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(cc0) (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] "! (GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)" "* return ret_cond_branch (operands[1], avr_jump_mode (operands[0], insn), 1);" [(set_attr "type" "branch1") (set_attr "cc" "clobber")])(define_insn "difficult_rvbranch" [(set (pc) (if_then_else (match_operator 1 "comparison_operator" [(cc0) (const_int 0)]) (pc) (label_ref (match_operand 0 "" ""))))] "(GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GTU || GET_CODE (operands[1]) == LE || GET_CODE (operands[1]) == LEU)" "* return ret_cond_branch (op
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