mips.h

gcc3.2.1源代码

#define TARGET_MIPS16		(target_flags & MASK_MIPS16)

/* Architecture target defines.  */
#define TARGET_MIPS3900             (mips_arch == PROCESSOR_R3900)
#define TARGET_MIPS4000             (mips_arch == PROCESSOR_R4000)
#define TARGET_MIPS4100             (mips_arch == PROCESSOR_R4100)
#define TARGET_MIPS4300             (mips_arch == PROCESSOR_R4300)
#define TARGET_MIPS4KC              (mips_arch == PROCESSOR_R4KC)
#define TARGET_MIPS5KC              (mips_arch == PROCESSOR_R5KC)

/* Scheduling target defines.  */
#define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
#define TUNE_MIPS3900               (mips_tune == PROCESSOR_R3900)
#define TUNE_MIPS4000               (mips_tune == PROCESSOR_R4000)
#define TUNE_MIPS5000               (mips_tune == PROCESSOR_R5000)
#define TUNE_MIPS6000               (mips_tune == PROCESSOR_R6000)

/* Macro to define tables used to set the flags.
   This is a list in braces of pairs in braces,
   each pair being { "NAME", VALUE }
   where VALUE is the bits to set or minus the bits to clear.
   An empty string NAME is used to identify the default VALUE.  */

#define TARGET_SWITCHES							\
{									\
  {"no-crt0",          0,                                               \
     N_("No default crt0.o") },					 	\
  {"int64",		  MASK_INT64 | MASK_LONG64,			\
     N_("Use 64-bit int type")},					\
  {"long64",		  MASK_LONG64,					\
     N_("Use 64-bit long type")},					\
  {"long32",		 -(MASK_LONG64 | MASK_INT64),			\
     N_("Use 32-bit long type")},					\
  {"split-addresses",	  MASK_SPLIT_ADDR,				\
     N_("Optimize lui/addiu address loads")},				\
  {"no-split-addresses", -MASK_SPLIT_ADDR,				\
     N_("Don't optimize lui/addiu address loads")},			\
  {"mips-as",		 -MASK_GAS,					\
     N_("Use MIPS as")},						\
  {"gas",		  MASK_GAS,					\
     N_("Use GNU as")},							\
  {"rnames",		  MASK_NAME_REGS,				\
     N_("Use symbolic register names")},				\
  {"no-rnames",		 -MASK_NAME_REGS,				\
     N_("Don't use symbolic register names")},				\
  {"gpOPT",		  MASK_GPOPT,					\
     N_("Use GP relative sdata/sbss sections")},			\
  {"gpopt",		  MASK_GPOPT,					\
     N_("Use GP relative sdata/sbss sections")},			\
  {"no-gpOPT",		 -MASK_GPOPT,					\
     N_("Don't use GP relative sdata/sbss sections")},			\
  {"no-gpopt",		 -MASK_GPOPT,					\
     N_("Don't use GP relative sdata/sbss sections")},			\
  {"stats",		  MASK_STATS,					\
     N_("Output compiler statistics")},					\
  {"no-stats",		 -MASK_STATS,					\
     N_("Don't output compiler statistics")},				\
  {"memcpy",		  MASK_MEMCPY,					\
     N_("Don't optimize block moves")},					\
  {"no-memcpy",		 -MASK_MEMCPY,					\
     N_("Optimize block moves")},					\
  {"mips-tfile",	  MASK_MIPS_TFILE,				\
     N_("Use mips-tfile asm postpass")},				\
  {"no-mips-tfile",	 -MASK_MIPS_TFILE,				\
     N_("Don't use mips-tfile asm postpass")},				\
  {"soft-float",	  MASK_SOFT_FLOAT,				\
     N_("Use software floating point")},				\
  {"hard-float",	 -MASK_SOFT_FLOAT,				\
     N_("Use hardware floating point")},				\
  {"fp64",		  MASK_FLOAT64,					\
     N_("Use 64-bit FP registers")},					\
  {"fp32",		 -MASK_FLOAT64,					\
     N_("Use 32-bit FP registers")},					\
  {"gp64",		  MASK_64BIT,					\
     N_("Use 64-bit general registers")},				\
  {"gp32",		 -MASK_64BIT,					\
     N_("Use 32-bit general registers")},				\
  {"abicalls",		  MASK_ABICALLS,				\
     N_("Use Irix PIC")},						\
  {"no-abicalls",	 -MASK_ABICALLS,				\
     N_("Don't use Irix PIC")},						\
  {"half-pic",		  MASK_HALF_PIC,				\
     N_("Use OSF PIC")},						\
  {"no-half-pic",	 -MASK_HALF_PIC,				\
     N_("Don't use OSF PIC")},						\
  {"long-calls",	  MASK_LONG_CALLS,				\
     N_("Use indirect calls")},						\
  {"no-long-calls",	 -MASK_LONG_CALLS,				\
     N_("Don't use indirect calls")},					\
  {"embedded-pic",	  MASK_EMBEDDED_PIC,				\
     N_("Use embedded PIC")},						\
  {"no-embedded-pic",	 -MASK_EMBEDDED_PIC,				\
     N_("Don't use embedded PIC")},					\
  {"embedded-data",	  MASK_EMBEDDED_DATA,				\
     N_("Use ROM instead of RAM")},					\
  {"no-embedded-data",	 -MASK_EMBEDDED_DATA,				\
     N_("Don't use ROM instead of RAM")},				\
  {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA,		\
     N_("Put uninitialized constants in ROM (needs -membedded-data)")},	\
  {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA,		\
     N_("Don't put uninitialized constants in ROM")},			\
  {"eb",		  MASK_BIG_ENDIAN,				\
     N_("Use big-endian byte order")},					\
  {"el",		 -MASK_BIG_ENDIAN,				\
     N_("Use little-endian byte order")},				\
  {"single-float",	  MASK_SINGLE_FLOAT,				\
     N_("Use single (32-bit) FP only")},				\
  {"double-float",	 -MASK_SINGLE_FLOAT,				\
     N_("Don't use single (32-bit) FP only")},				\
  {"mad",		  MASK_MAD,					\
     N_("Use multiply accumulate")},					\
  {"no-mad",		 -MASK_MAD,					\
     N_("Don't use multiply accumulate")},				\
  {"no-fused-madd",       MASK_NO_FUSED_MADD,                           \
     N_("Don't generate fused multiply/add instructions")},		\
  {"fused-madd",         -MASK_NO_FUSED_MADD,                           \
     N_("Generate fused multiply/add instructions")},			\
  {"fix4300",             MASK_4300_MUL_FIX,				\
     N_("Work around early 4300 hardware bug")},			\
  {"no-fix4300",         -MASK_4300_MUL_FIX,				\
     N_("Don't work around early 4300 hardware bug")},			\
  {"3900",		  0,				                \
     N_("Optimize for 3900")},						\
  {"4650",		  0,                    			\
     N_("Optimize for 4650")},						\
  {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV,			\
     N_("Trap on integer divide by zero")},				\
  {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV,			\
     N_("Don't trap on integer divide by zero")},			\
  {"check-range-division",MASK_CHECK_RANGE_DIV,				\
     N_("Trap on integer divide overflow")},				\
  {"no-check-range-division",-MASK_CHECK_RANGE_DIV,			\
     N_("Don't trap on integer divide overflow")},			\
  {"debug",		  MASK_DEBUG,					\
     NULL},								\
  {"debuga",		  MASK_DEBUG_A,					\
     NULL},								\
  {"debugb",		  MASK_DEBUG_B,					\
     NULL},								\
  {"debugc",		  MASK_DEBUG_C,					\
     NULL},								\
  {"debugd",		  MASK_DEBUG_D,					\
     NULL},								\
  {"debuge",		  MASK_DEBUG_E,					\
     NULL},								\
  {"debugf",		  MASK_DEBUG_F,					\
     NULL},								\
  {"debugg",		  MASK_DEBUG_G,					\
     NULL},								\
  {"debugh",		  MASK_DEBUG_H,					\
     NULL},								\
  {"debugi",		  MASK_DEBUG_I,					\
     NULL},								\
  {"",			  (TARGET_DEFAULT				\
			   | TARGET_CPU_DEFAULT				\
			   | TARGET_ENDIAN_DEFAULT),			\
     NULL},								\
}

/* Default target_flags if no switches are specified  */

#ifndef TARGET_DEFAULT
#define TARGET_DEFAULT 0
#endif

#ifndef TARGET_CPU_DEFAULT
#define TARGET_CPU_DEFAULT 0
#endif

#ifndef TARGET_ENDIAN_DEFAULT
#ifndef DECSTATION
#define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
#else
#define TARGET_ENDIAN_DEFAULT 0
#endif
#endif

#ifndef MIPS_ISA_DEFAULT
#define MIPS_ISA_DEFAULT 1
#endif

#ifdef IN_LIBGCC2
#undef TARGET_64BIT
/* Make this compile time constant for libgcc2 */
#ifdef __mips64
#define TARGET_64BIT		1
#else
#define TARGET_64BIT		0
#endif
#endif /* IN_LIBGCC2 */

#ifndef MULTILIB_ENDIAN_DEFAULT
#if TARGET_ENDIAN_DEFAULT == 0
#define MULTILIB_ENDIAN_DEFAULT "EL"
#else
#define MULTILIB_ENDIAN_DEFAULT "EB"
#endif
#endif

#ifndef MULTILIB_ISA_DEFAULT
#  if MIPS_ISA_DEFAULT == 1
#    define MULTILIB_ISA_DEFAULT "mips1"
#  else
#    if MIPS_ISA_DEFAULT == 2
#      define MULTILIB_ISA_DEFAULT "mips2"
#    else
#      if MIPS_ISA_DEFAULT == 3
#        define MULTILIB_ISA_DEFAULT "mips3"
#      else
#        if MIPS_ISA_DEFAULT == 4
#          define MULTILIB_ISA_DEFAULT "mips4"
#        else
#          if MIPS_ISA_DEFAULT == 32
#            define MULTILIB_ISA_DEFAULT "mips32"
#          else
#            if MIPS_ISA_DEFAULT == 64
#              define MULTILIB_ISA_DEFAULT "mips64"
#            else
#          define MULTILIB_ISA_DEFAULT "mips1"
#         endif
#        endif
#       endif
#      endif
#    endif
#  endif
#endif

#ifndef MULTILIB_DEFAULTS
#define MULTILIB_DEFAULTS { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT }
#endif

/* We must pass -EL to the linker by default for little endian embedded
   targets using linker scripts with a OUTPUT_FORMAT line.  Otherwise, the
   linker will default to using big-endian output files.  The OUTPUT_FORMAT
   line must be in the linker script, otherwise -EB/-EL will not work.  */

#ifndef ENDIAN_SPEC
#if TARGET_ENDIAN_DEFAULT == 0
#define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
#else
#define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
#endif
#endif

#define TARGET_OPTIONS							\
{									\
  SUBTARGET_TARGET_OPTIONS						\
  { "cpu=",	&mips_cpu_string,					\
      N_("Specify CPU for scheduling purposes")},			\
  { "tune=",    &mips_tune_string,                                   \
      N_("Specify CPU for scheduling purposes")},                       \
  { "arch=",    &mips_arch_string,                                      \
      N_("Specify CPU for code generation purposes")},                  \
  { "ips",	&mips_isa_string,					\
      N_("Specify a Standard MIPS ISA")},				\
  { "entry",	&mips_entry_string,					\
      N_("Use mips16 entry/exit psuedo ops")},				\
  { "no-mips16", &mips_no_mips16_string,				\
      N_("Don't use MIPS16 instructions")},				\
  { "explicit-type-size", &mips_explicit_type_size_string,		\
      NULL},								\
  { "no-flush-func", &mips_cache_flush_func,				\
      N_("Don't call any cache flush functions")},			\
  { "flush-func=", &mips_cache_flush_func,				\
      N_("Specify cache flush function")},				\
}

/* This is meant to be redefined in the host dependent files.  */
#define SUBTARGET_TARGET_OPTIONS

#define GENERATE_BRANCHLIKELY  (!TARGET_MIPS16 && ISA_HAS_BRANCHLIKELY)

/* Generate three-operand multiply instructions for SImode.  */
#define GENERATE_MULT3_SI       ((TARGET_MIPS3900                       \
                                  || mips_isa == 32                     \
                                  || mips_isa == 64)                    \
                                 && !TARGET_MIPS16)

/* Generate three-operand multiply instructions for DImode.  */
#define GENERATE_MULT3_DI       ((TARGET_MIPS3900)                      \
				 && !TARGET_MIPS16)

/* Macros to decide whether certain features are available or not,
   depending on the instruction set architecture level.  */

#define BRANCH_LIKELY_P()	GENERATE_BRANCHLIKELY
#define HAVE_SQRT_P()		(mips_isa != 1)

/* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3).  */
#define ISA_HAS_64BIT_REGS	(mips_isa == 3          \
				 || mips_isa == 4 	\
                                 || mips_isa == 64)

/* ISA has branch likely instructions (eg. mips2).  */
/* Disable branchlikely for tx39 until compare rewrite.  They haven't
   been generated up to this point.  */
#define ISA_HAS_BRANCHLIKELY	(mips_isa != 1                          \
				 /* || TARGET_MIPS3900 */)

/* ISA has the conditional move instructions introduced in mips4.  */
#define ISA_HAS_CONDMOVE        (mips_isa == 4				\
				 || mips_isa == 32                      \
				 || mips_isa == 64)

/* ISA has just the integer condition move instructions (movn,movz) */
#define ISA_HAS_INT_CONDMOVE     0



/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
   branch on CC, and move (both FP and non-FP) on CC.  */
#define ISA_HAS_8CC		(mips_isa == 4				\
                         	 || mips_isa == 32                      \
				 || mips_isa == 64)


/* This is a catch all for the other new mips4 instructions: indexed load and
   indexed prefetch instructions, the FP madd,msub,nmadd, and nmsub instructions,
   and the FP recip and recip sqrt instructions */
#define ISA_HAS_FP4             (mips_isa == 4				\
				)

/* ISA has conditional trap instructions.  */
#define ISA_HAS_COND_TRAP	(mips_isa >= 2)

/* ISA has multiply-accumulate instructions, madd and msub.  */
#define ISA_HAS_MADD_MSUB       (mips_isa == 32                         \
                                || mips_isa == 64                       \
                                )

/* ISA has nmadd and nmsub instructions.  */
#define ISA_HAS_NMADD_NMSUB	(mips_isa == 4				\
				)

/* ISA has count leading zeroes/ones instruction (not implemented).  */
#define ISA_HAS_CLZ_CLO         (mips_isa == 32                         \
                                || mips_isa == 64                       \
                                )

/* ISA has double-word count leading zeroes/ones instruction (not
   implemented).  */