s390.md

gcc3.2.1源代码

{
  int part = s390_single_qi (operands[1], SImode, 0);
  operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part));

  operands[0] = gen_rtx_MEM (QImode, 
			     plus_constant (XEXP (operands[0], 0), part));
  return \"tm\\t%0,%b1\";
}"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*ltr"
  [(set (reg 33)
        (compare (match_operand:SI 0 "register_operand" "d")
                 (match_operand:SI 1 "const0_operand" "")))
   (set (match_operand:SI 2 "register_operand" "=d")
        (match_dup 0))]
  "s390_match_ccmode(insn, CCSmode)"
  "ltr\\t%2,%0"
  [(set_attr "op_type" "RR")])

(define_insn "*icm15"
  [(set (reg 33)
        (compare (match_operand:SI 0 "s_operand" "Qo")
                 (match_operand:SI 1 "const0_operand" "")))
   (set (match_operand:SI 2 "register_operand" "=d")
        (match_dup 0))]
  "s390_match_ccmode(insn, CCSmode)"
  "icm\\t%2,15,%0"
  [(set_attr "op_type" "RS")
   (set_attr "atype"   "mem")])

(define_insn "*icm15_cconly"
  [(set (reg 33)
        (compare (match_operand:SI 0 "s_operand" "Qo")
                 (match_operand:SI 1 "const0_operand" "")))
   (clobber (match_scratch:SI 2 "=d"))]
  "s390_match_ccmode(insn, CCSmode)"
  "icm\\t%2,15,%0"
  [(set_attr "op_type" "RS")
   (set_attr "atype"   "mem")])

(define_insn "*cmpsi_ccs_0"
  [(set (reg 33)
        (compare (match_operand:SI 0 "register_operand" "d")
                 (match_operand:SI 1 "const0_operand" "")))]
  "s390_match_ccmode(insn, CCSmode)"
  "ltr\\t%0,%0"
  [(set_attr "op_type" "RR")])

(define_insn "*cmpsidi_ccs"
  [(set (reg 33)
        (compare (match_operand:SI 0 "register_operand" "d")
                 (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))]
  "s390_match_ccmode(insn, CCSmode)"
  "ch\\t%0,%1"
  [(set_attr "op_type" "RR")
   (set_attr "atype"   "mem")])

(define_insn "*cmpsi_ccs"
  [(set (reg 33)
        (compare (match_operand:SI 0 "register_operand" "d,d,d")
                 (match_operand:SI 1 "general_operand" "d,K,m")))]
  "s390_match_ccmode(insn, CCSmode)"
  "@
   cr\\t%0,%1
   chi\\t%0,%c1
   c\\t%0,%1"
  [(set_attr "op_type" "RR,RI,RX")
   (set_attr "atype"   "reg,reg,mem")])
   
(define_insn "*cmpsi_ccu"
  [(set (reg 33)
        (compare (match_operand:SI 0 "register_operand" "d,d")
                 (match_operand:SI 1 "general_operand" "d,m")))]
  "s390_match_ccmode(insn, CCUmode)"
  "@
   clr\\t%0,%1
   cl\\t%0,%1"
  [(set_attr "op_type" "RR,RX")
   (set_attr "atype"   "reg,mem")])

(define_insn "*cmpsi_ccu_mem"
  [(set (reg 33)
        (compare (match_operand:SI 0 "s_operand" "oQ")
                 (match_operand:SI 1 "s_imm_operand" "oQ")))]
  "s390_match_ccmode(insn, CCUmode)"
  "clc\\t%O0(4,%R0),%1"
   [(set_attr "op_type" "SS")
    (set_attr "atype"   "mem")])


; HI instructions

(define_insn "*cmphi_tm_sub"
  [(set (reg 33)
        (compare (and:SI (subreg:SI (match_operand:HI 0 "s_operand" "%Qo") 0)
                         (match_operand:SI 1 "immediate_operand" "n"))
                 (const_int 0)))]
  "s390_match_ccmode(insn, CCTmode)
   && s390_single_qi (operands[1], HImode, 0) >= 0"
  "*
{
  int part = s390_single_qi (operands[1], HImode, 0);
  operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part));

  operands[0] = gen_rtx_MEM (QImode, 
			     plus_constant (XEXP (operands[0], 0), part));
  return \"tm\\t%0,%b1\";
}"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*icm3"
  [(set (reg 33)
        (compare (match_operand:HI 0 "s_operand" "Qo")
                 (match_operand:HI 1 "const0_operand" "")))
   (set (match_operand:HI 2 "register_operand" "=d")
        (match_dup 0))]
  "s390_match_ccmode(insn, CCSmode)"
  "icm\\t%2,3,%0"
  [(set_attr "op_type" "RS")
   (set_attr "atype"   "mem")])

(define_insn "*cmphi_cct_0"
  [(set (reg 33)
        (compare (match_operand:HI 0 "register_operand" "d")
                 (match_operand:HI 1 "const0_operand"   "")))]
  "s390_match_ccmode(insn, CCTmode)"
  "tml\\t%0,65535"
  [(set_attr "op_type" "RX")])

(define_insn "*cmphi_ccs_0"
  [(set (reg 33)
        (compare (match_operand:HI 0 "s_operand" "Qo")
                 (match_operand:HI 1 "const0_operand" "")))
   (clobber (match_scratch:HI 2 "=d"))]
  "s390_match_ccmode(insn, CCSmode)"
  "icm\\t%2,3,%0"
  [(set_attr "op_type" "RS")
   (set_attr "atype"   "mem")])

(define_insn "*cmphi_ccu"
  [(set (reg 33)
        (compare (match_operand:HI 0 "register_operand" "d")
                 (match_operand:HI 1 "s_imm_operand" "Qo")))]
  "s390_match_ccmode(insn, CCUmode)"
  "clm\\t%0,3,%1"
  [(set_attr "op_type" "RS")
   (set_attr "atype"   "mem")])

(define_insn "*cmphi_ccu_mem"
  [(set (reg 33)
        (compare (match_operand:HI 0 "s_operand" "oQ")
                 (match_operand:HI 1 "s_imm_operand" "oQ")))]
  "s390_match_ccmode(insn, CCUmode)"
  "clc\\t%O0(2,%R0),%1"
  [(set_attr "op_type" "SS")
   (set_attr "atype"   "mem")])


; QI instructions

(define_insn "*cmpqi_tm2"
  [(set (reg 33)
        (compare (zero_extract:SI (match_operand:QI 0 "s_operand" "Qo")
	                          (match_operand:SI 1 "const_int_operand" "n")
                                  (match_operand:SI 2 "const_int_operand" "n"))
                 (const_int 0)))]
  "s390_match_ccmode(insn, CCTmode)
   && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 
   && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
  "*
{
  int block = (1 << INTVAL (operands[1])) - 1;
  int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);

  operands[2] = GEN_INT (block << shift);
  return \"tm\\t%0,%b2\";
}"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*cmpqi_tm"
  [(set (reg 33)
        (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,Q")
                         (match_operand:QI 1 "immediate_operand" "n,n"))
                 (const_int 0)))]
  "s390_match_ccmode(insn, CCTmode)"
  "@
   tml\\t%0,%b1
   tm\\t%0,%b1"
  [(set_attr "op_type" "RI,SI")
   (set_attr "atype"   "reg,mem")])

(define_insn "*cmpqi_tm_sub"
  [(set (reg 33)
        (compare (and:SI (subreg:SI (match_operand:QI 0 "s_operand" "%Qo") 0)
                         (match_operand:SI 1 "immediate_operand" "n"))
                 (const_int 0)))]
  "s390_match_ccmode(insn, CCTmode)"
  "tm\\t%0,%b1"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*icm1"
  [(set (reg 33)
        (compare (match_operand:QI 0 "s_operand" "Qo")
                 (match_operand:QI 1 "const0_operand" "")))
   (set (match_operand:QI 2 "register_operand" "=d")
        (match_dup 0))]
  "s390_match_ccmode(insn, CCSmode)"
  "icm\\t%2,1,%0"
  [(set_attr "op_type" "RS")
   (set_attr "atype"   "mem")])

(define_insn "*tm_0"
  [(set (reg 33)
        (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo")
                                         (match_operand:QI 1 "immediate_operand" "")))
                 (const_int 0)))]
  "s390_match_ccmode(insn, CCTmode) &&
   INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
  "tm\\t%0,%1"
  [(set_attr "op_type" "RI")
   (set_attr "atype"   "mem")])

(define_insn "*cmpqi_cct_0"
  [(set (reg 33)
        (compare (match_operand:QI 0 "register_operand" "d")
                 (match_operand:QI 1 "const0_operand"   "")))]
  "s390_match_ccmode(insn, CCTmode)"
  "tml\\t%0,255"
  [(set_attr "op_type" "RI")])

(define_insn "*cmpqi_ccs_0"
  [(set (reg 33)
        (compare (match_operand:QI 0 "s_operand" "Qo")
                 (match_operand:QI 1 "const0_operand" "")))
   (clobber (match_scratch:QI 2 "=d"))]
  "s390_match_ccmode(insn, CCSmode)"
  "icm\\t%2,1,%0"
  [(set_attr "op_type" "RS")
   (set_attr "atype"   "mem")])

(define_insn "*cmpqi_ccu_0"
  [(set (reg 33)
        (compare (match_operand:QI 0 "s_operand"      "Qo")
                 (match_operand:QI 1 "const0_operand" "")))]
  "s390_match_ccmode(insn, CCUmode)"
  "cli\\t%0,0"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*cmpqi_ccu"
  [(set (reg 33)
        (compare (match_operand:QI 0 "register_operand" "d")
                 (match_operand:QI 1 "s_imm_operand" "Qo")))]
  "s390_match_ccmode(insn, CCUmode)"
  "clm\\t%0,1,%1"
  [(set_attr "op_type" "RS")
   (set_attr "atype"   "mem")])

(define_insn "*cmpqi_ccu_immed"
  [(set (reg 33)
        (compare (match_operand:QI 0 "s_operand" "Qo")
                 (match_operand:QI 1 "const_int_operand" "n")))]
  "s390_match_ccmode(insn, CCUmode) &&
   INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256"
  "cli\\t%0,%1"
  [(set_attr "op_type" "SI")
   (set_attr "atype"   "mem")])

(define_insn "*cmpqi_ccu_mem"
  [(set (reg 33)
        (compare (match_operand:QI 0 "s_operand" "oQ")
                 (match_operand:QI 1 "s_imm_operand" "oQ")))]
  "s390_match_ccmode(insn, CCUmode)"
  "clc\\t%O0(1,%R0),%1"
  [(set_attr "op_type" "SS")
   (set_attr "atype"   "mem")])


; DF instructions

(define_insn "*cmpdf_ccs_0"
  [(set (reg 33)
        (compare (match_operand:DF 0 "register_operand" "f")
                 (match_operand:DF 1 "const0_operand" "")))]
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
  "ltdbr\\t%0,%0"
   [(set_attr "op_type" "RRE")])

(define_insn "*cmpdf_ccs_0_ibm"
  [(set (reg 33)
        (compare (match_operand:DF 0 "register_operand" "f")
                 (match_operand:DF 1 "const0_operand" "")))]
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
  "ltdr\\t%0,%0"
   [(set_attr "op_type" "RR")])

(define_insn "*cmpdf_ccs"
  [(set (reg 33)
        (compare (match_operand:DF 0 "register_operand" "f,f")
                 (match_operand:DF 1 "general_operand" "f,m")))]
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
  "@
   cdbr\\t%0,%1
   cdb\\t%0,%1"
   [(set_attr "op_type" "RRE,RXE")
    (set_attr "atype"   "reg,mem")])  

(define_insn "*cmpdf_ccs_ibm"
  [(set (reg 33)
        (compare (match_operand:DF 0 "register_operand" "f,f")
                 (match_operand:DF 1 "general_operand" "f,m")))]
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
  "@
   cdr\\t%0,%1
   cd\\t%0,%1"
   [(set_attr "op_type" "RR,RX")
    (set_attr "atype"   "reg,mem")])  


; SF instructions

(define_insn "*cmpsf_ccs_0"
  [(set (reg 33)
        (compare (match_operand:SF 0 "register_operand" "f")
                 (match_operand:SF 1 "const0_operand" "")))]
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
  "ltebr\\t%0,%0"
   [(set_attr "op_type" "RRE")])

(define_insn "*cmpsf_ccs_0_ibm"
  [(set (reg 33)
        (compare (match_operand:SF 0 "register_operand" "f")
                 (match_operand:SF 1 "const0_operand" "")))]
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
  "lter\\t%0,%0"
   [(set_attr "op_type" "RR")])

(define_insn "*cmpsf_ccs"
  [(set (reg 33)
        (compare (match_operand:SF 0 "register_operand" "f,f")
                 (match_operand:SF 1 "general_operand" "f,m")))]
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
  "@
   cebr\\t%0,%1
   ceb\\t%0,%1"
  [(set_attr "op_type" "RRE,RXE")
   (set_attr "atype"   "reg,mem")])

(define_insn "*cmpsf_ccs"
  [(set (reg 33)
        (compare (match_operand:SF 0 "register_operand" "f,f")
                 (match_operand:SF 1 "general_operand" "f,m")))]
  "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
  "@
   cer\\t%0,%1
   ce\\t%0,%1"
  [(set_attr "op_type" "RR,RX")
   (set_attr "atype"   "reg,mem")])


;;
;;- Move instructions.
;;

;
; movti instruction pattern(s).
;

(define_insn "*movti_ss"
  [(set (match_operand:TI 0 "s_operand" "=Qo")
        (match_operand:TI 1 "s_imm_operand" "Qo"))]
  ""
  "mvc\\t%O0(16,%R0),%1"	
  [(set_attr "op_type" "SS")
   (set_attr "atype"   "mem")])

(define_insn "movti"
  [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m")
        (match_operand:TI 1 "general_operand" "Q,d,dKm,d"))]
  "TARGET_64BIT"
  "@
   lmg\\t%0,%N0,%1
   stmg\\t%1,%N1,%0
   #
   #"
  [(set_attr "op_type" "RSE,RSE,NN,NN")
   (set_attr "atype"   "mem")])

(define_split
  [(set (match_operand:TI 0 "nonimmediate_operand" "")
        (match_operand:TI 1 "general_operand" ""))]
  "TARGET_64BIT && reload_completed
   && !s_operand (operands[0], VOIDmode)
   && !s_operand (operands[1], VOIDmode)
   && (register_operand (operands[0], VOIDmode)
       || register_operand (operands[1], VOIDmode))
   && (!register_operand (operands[0], VOIDmode)
       || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
                                    operands[1])
       || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode),
                                    operands[1]))"
  [(set (match_dup 2) (match_dup 4))
   (set (match_dup 3) (match_dup 5))]
  "
{
  if (!register_operand (operands[0], VOIDmode)
      || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode),
                                   operands[1]))
    {
      operands[2] = operand_subword (operands[0], 0, 0, TImode);
      operands[3] = operand_subword (operands[0], 1, 0, TImode);
      operands[4] = operand_subword (operands[1], 0, 0, TImode);
      operands[5] = operand_subword (operands[1], 1, 0, TImode);
    }
  else
    {
      operands[2] = operand_subword (operands[0], 1, 0, TImode);
      operands[3] = operand_subword (operands[0], 0, 0, TImode);
      operands[4] = operand_subword (operands[1], 1, 0, TImode);
      operands[5] = operand_subword (operands[1], 0, 0, TImode);
    }
}")

(define_split
  [(set (match_operand:TI 0 "register_operand" "")
        (match_operand:TI 1 "memory_operand" ""))]
  "TARGET_64BIT && reload_completed
   && !s_operand (operands[1], VOIDmode)"