bdmr4101.htm

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

<title>BDMR4101</title>
<h1 align=center>BDMR4101</h1>
<!--INDEX "LR4101 Evaluation Board" BDMR4101 4101 2681 Sonic -->
<!--INDEX "TinyRISC Evaluation Board" uMeteor -->

</dl><h2>Description</h2><dl><dd>

The BDMR4101 is the evaluation board for the 4101 TinyRISC Processor. It
comes with it's own special power supply.<p>

</dl><h2>Memory Map</h2><dl><dd>
<pre>
	RAM	   a000.0000 1MB
		   a100.0000 8MB Module (optional)
	ROM	   bfc0.0000 4 flash sockets U5,U6,U7,U8
	DUART	   be00.0000 2681
	Ethernet   Sonic 10BaseT only
</pre>

</dl><h2>Interrupts</h2><dl><dd>
<pre>
	int0	2681
	int1	Sonic
	int2	SerialICE Port + external pin if CFG:CPC0EN=1
	int3	external pin if CFG:CPC1EN=1
	int4	external pin if CFG:CPC2EN=1
	int5	external pin if CFG:CPC3EN=1
</pre>

</dl><h2>External Connections</h2><dl><dd>
<pre>
	Power - 5V DC via coaxial power connector
	RS232
		J28 ChanA (PMON console)
		J27 ChanB
	SerialICE Port
</pre>

</dl><h2>Clocks</h2><dl><dd>
<dl>
<dt><b>U52</b></dt><dd>Clock for CPU.
<dt><b>U53</b></dt><dd>Clock for SerialICE Port. 
1.8432MHz=115200, 20MHz=1250000.
</dl>

</dl><h2>Jumpers</h2><dl><dd>

<table border cellpadding=5>
<tr><th></th><th>Jumper In</th><th>		Jumper Out</th></tr>

<tr><td valign=top>
J1	</td><td>Little Endian		</td><td><b>Big Endian</b>
</td></tr><tr><td valign=top>
J2	</td><td><b>Wburstn</b>		</td><td>-
</td></tr><tr><td valign=top>
J3	</td><td>No Dwrap		</td><td><b>Dwrap</b>
</td></tr><tr><td valign=top>
J4	</td><td><b>No Iwrap</b>		</td><td>Iwrap
</td></tr><tr><td valign=top>
J5-J6	</td><td colspan=2>Sram wait states
	<dl>
	<dd><b>0 ws (J6=In J5=In)</b>
	<dd>1 ws (J6=In J5=Out)
	<dd>2 ws (J6=Out J5=In)
	<dd>3 ws (J6=Out J5=Out)
	</dl>
</td></tr><tr><td valign=top>
J7	</td><td>BCLK=PCLK		</td><td><b>BCLK=0.5*PCLK</b>
</td></tr><tr><td>
J8	</td><td><b>Arb_mode1</b>		</td><td>Arb_mode2
</td></tr><tr><td valign=top>
J9,J11	</td><td colspan=2>Icache refill size
	<dl>
	<dd>1 word (J9=In J11=In)
	<dd>2 word (J9=In J11=Out)
	<dd>4 word (J9=Out J11=In)
	<dd><b>8 word (J9=Out J11=Out)</b>
	</dl>
</td></tr><tr><td valign=top>
J10,J12	</td><td><b>Default</b>		</td><td>-
</td></tr><tr><td valign=top>
J13,J15	</td><td colspan=2>Dcache refill size
	<dl>
	<dd>1 word (J13=In J15=In)
	<dd>2 word (J13=In J15=Out)
	<dd><b>4 word (J13=Out J15=In)</b>
	<dd>8 word (J13=Out J15=Out)
	</dl>
</td></tr><tr><td valign=top>
J14,J16	</td><td><b>Default</b>		</td><td>-
</td></tr><tr><td valign=top>
J17-J18	</td><td><b>on board 3.3v</b>		</td><td>external 3.3v
</td></tr><tr><td valign=top>
J19	</td><td><b>Default Position 1-2</b>		</td><td>-
</td></tr><tr><td valign=top>
J20		</td><td>-	</td><td>Sonic Status

</td></tr><tr><td valign=top>
J25</td><td>1-2 SerialICE Port Clock comes from oscillator (U53)
</td><td>2-3 SerialICE Port Clock comes from SerialICE Port connector.
A board will always transmit it's osc clock to the connector.
It is swapped with the clock input on the other board in the cable.

</td></tr><tr><td valign=top>
J26</td><td>in - J27 (tty1 connector) acts as tty1. SerialICE uses 
SerialICE Port connector.
</td><td>
out - J27 is connected to the SerialICE Port through level translators
and tty1 is unavailable. This requires that the onboard osc be
selected and installed.

</td></tr></table>

</dl><h2>IceKernel</h2><dl><dd>
<ul>
<li>For the wiggler, J25 1-2, J26 in.
<li>For tty1, J25 1-2, J26 out.
</ul>


</dl><p><hr>
<b>Navigation:</b> 
<a href="index.htm">Document Home</a> | 
<a href="doctoc.htm">Document Contents</a> | 
<a href="docindex.htm">Document Index</a> <p>