bdmr4102.htm

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

<title>BDMR4102</title>
<h1 align=center>BDMR4102</h1>
<!--INDEX "LR4102 Evaluation Board" BDMR4102 4102 -->
<!--INDEX 16550 Am79C970A Am29F080 TinyRISC EJTAG -->

</dl><h2>Description</h2><dl><dd>

The BDMR4102 is the evaluation board for the 4102 TinyRISC Processor. It
comes with it's own special power supply.<p>

</dl><h2>Memory Map</h2><dl><dd>

On the LR4102, the memory map is determined by how the chip-select
registers have been programmed.  The only thing that's fixed is the GP
number to which each peripheral is connected.<p>

<pre>
	RAM	   GP3 SRAM 128KB
		   GP2 SDRAM 16MB Module (optional) (must be located
		   on a 32MB boundary).
	ROM	   GP0 1 eprom socket
		   bfd0.0000 when not configured as boot device
	DUART	   GP4 16550
	Flash	   GP0 29F080 1MB. 
		   bfd0.0000 when not configured as boot device
	Ethernet   PCI AMD 79C970A 10BaseT only
</pre>

</dl><h2>Interrupts</h2><dl><dd>
<pre>
	int0	?
	int1	timer0
	int2	SerialICE Port
	int3	timer1+(16550 scr1:cpc1en=1)
	int4	Am79C970A Ethernet
	int5	?
</pre>

</dl><h2>External Connections</h2><dl><dd>
<pre>
	Power - 5V DC via coaxial power connector
	RS232
		J10 16550 (PMON console)
		J9  SerialICE Port via level shifters
	SerialICE 
		J8 SerialICE Port direct
</pre>

</dl><h2>Clocks</h2><dl><dd>
<dl>
<dt><b>U?</b></dt><dd>Clock for CPU.
<dt><b>U6</b></dt><dd>Clock for SerialICE Port. 
1.8432MHz=115200, 20MHz=1250000.
</dl>

</dl><h2>Jumpers</h2><dl><dd>

<table border cellpadding=5>
<tr><th></th><th>Jumper In</th><th>		Jumper Out</th></tr>

<tr><td valign=top>
JP6	</td><td>Little Endian		</td><td>Big Endian
</td></tr><tr><td valign=top>
JP9	</td><td>Boot from EPROM</td><td>Boot from flash

</td></tr><tr><td valign=top>
JP15</td><td valign=top>
1-2 - J9 is connected to the SerialICE Port through level translators.
This requires that the onboard osc be selected and installed.
</td><td valign=top>
2-3 - Connect J8 (the SerialICE header) to the SerialICE Port. 

</td></tr><tr><td valign=top>
JP16</td><td>1-2 SerialICE Port Clock comes from oscillator (U6)
</td><td>2-3 SerialICE Port Clock comes from SerialICE Port connector.
A board will always transmit it's osc clock to the connector.
It is swapped with the clock input on the other board in the cable.

</td></tr></table>

</dl><h2>IceKernel</h2><dl><dd>
<ul>
<li>For the wiggler: JP15 2-3, JP16 1-2.
<li>For tty1: JP15 1-2, JP16 1-2.
</ul>

</dl><h2>Seven-segment Display</h2><dl><dd>


Address: UART base + 0x20<p>
<pre>

          01
	-----
     20	|   | 02
	-----  40
     10	|   | 04
	-----  o 80
	  08
</pre>

Note: the specified value turns the selected segment off.<p>



</dl><p><hr>
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