401x.c

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

		printf("%s: too many args\n",av[i]);
		return;
		}
	}
if (n==0) set = 0;
if (n<2) adr = next_adr;

if (iflag) {
	cachetag = ICACHETAG;
	cacheram = ICACHERAM;
	cache_size = icache_size;
	}
else {
	cachetag = DCACHETAG;
	cacheram = DCACHERAM;
	cache_size = dcache_size;
	}

/* cache lines always start on 32-byte boundaries */
adr &= ~(cache_line_size-1); 

printf("Displaying %s set %d\n",(iflag)?"icache":"dcache",set);

ccc = read_target(XT_CP0,C0_CCC,0);
if (    (iflag && set == 1 && ccc&CCC_ISR1) ||
	(!iflag && set == 0 && ccc&CCC_SR0) ||
	(!iflag && set == 1 && ccc&CCC_SR1))
		printf("This set is in scatchpad mode\n");

for (n=j=0;j<8;adr += cache_line_size,n++) {
	if (n > cache_size/cache_line_size) break;
	tag = readCache_401x(set,cachetag,adr);
	if (vflag && (tag&VALID_BIT)==0) continue;
	printf("%08x  %08x ",adr,readCache_401x(set,cacheram,adr));
	printf("%08x ",readCache_401x(set,cacheram,adr+4));
	printf("%08x ",readCache_401x(set,cacheram,adr+8));
	printf("%08x\n          ",readCache_401x(set,cacheram,adr+12));
	printf("%08x ",readCache_401x(set,cacheram,adr+16));
	printf("%08x ",readCache_401x(set,cacheram,adr+20));
	printf("%08x ",readCache_401x(set,cacheram,adr+24));
	printf("%08x ",readCache_401x(set,cacheram,adr+28));
	printf(" %08x\n",tag);
	j++;
	}
next_adr = adr;
}
#endif

/*************************************************************
*  void setupcacheline_401x(addr)
*	Switch the icache set1 to scratchpad mode.
*	Copy real memory bytes to the correct line.
*	Write the correct tag and valid bit.
*	Exit with ISR1 set.
*/
void setupcacheline_401x(addr)
Ulong addr;
{
Ulong ccc,tmpcfg,addrmsk;
int n;

ccc = read_target(XT_CP0,C0_CCC,0);
ccc |= (CCC_IE1|CCC_IS8);
tmpcfg = ccc;
tmpcfg &= ~(CCC_IE0|CCC_DE0|CCC_DE1|CCC_IE1);

/* copy data from memory */
writeGpr(8,addr&~0x1f);
writeGpr(9,K1BASE|addr&~0x1f);
writeGpr(10,8);

n = 1; /* start of loop */
n += writeGpr(4,ccc);
n += send_instr(MTC0(4,C0_CCC)); /* 3 nops before ld or st */
n += send_instr(0);
n += send_instr(0);
n += send_instr(0);
n += send_instr(LW(2,0,9));

n += writeGpr(4,tmpcfg|CCC_ISC|CCC_IE1);
n += send_instr(MTC0(4,C0_CCC)); /* 3 nops before ld or st */
n += send_instr(0);
n += send_instr(ADDIU(9,9,4));
n += send_instr(SUBIU(10,1));
n += send_instr(SW(2,0,8));
n += send_instr(BNE(10,0,0-n));
send_instr(ADDIU(8,8,4));
/* end of loop */

/* write the tag */
writeGpr(8,tmpcfg|CCC_TAG|CCC_ISC|CCC_IE1);
send_instr(MTC0(8,C0_CCC)); /* 3 nops before ld or st */
send_instr(0);
writeGpr(9,addr);
addrmsk = (0x7<<29)|((8*1024)-1);
writeGpr(8,(addr&~addrmsk)|VALID_BIT);
send_instr(SW(8,0,9));

/* restore CCC */
writeGpr(8,ccc|CCC_ISR1|CCC_IE1);
send_instr(MTC0(8,C0_CCC)); /* 3 nops before ld or st */
send_instr(0);
send_instr(0);
readA0();
}

/*************************************************************
*  void wrwdtocache_401x(addr,val)
*	Writes one word to the iscratchpad. 
*	Assumes that setupcacheline() has already been called.
*/
void wrwdtocache_401x(addr,val)
Ulong addr,val;
{
Ulong ccc,tmpcfg;

ccc = read_target(XT_CP0,C0_CCC,0);
tmpcfg = ccc;
tmpcfg &= ~(CCC_IE0|CCC_DE0|CCC_DE1|CCC_ISR1);
tmpcfg |= CCC_ISC;
writeGpr(8,tmpcfg);
send_instr(MTC0(8,C0_CCC)); /* 3 nops before ld or st */
send_instr(0);

writeGpr(8,val);
writeGpr(9,addr);
send_instr(SW(8,0,9));

/* restore CCC */
writeGpr(8,ccc);
send_instr(MTC0(8,C0_CCC)); /* 3 nops before ld or st */
send_instr(0);
send_instr(0);
readA0();
}

/*************************************************************
*  int ilockReq_401x(addr)
*	verify that other ilock bpts don't conflict with this one
*		(ie. are a cachesize multiple apart).
*	Also verify that ISR1 bit is not already set.
*/
int ilockReq_401x(addr)
Ulong addr;
{
Ulong tmsk,omsk;
int i;

/* return error if instr scratchpad ram is in use */
if (read_target(XT_CP0,C0_CCC,0)&CCC_ISR1) return(0); 

tmsk = (icache_size)-1; /* tag mask */
omsk = tmsk&~(16-1); /* offset mask: line size 16B */
for (i=0;i<MAX_BPT;i++) {
	if (brkList[i].type==0) continue;
	if (brkList[i].method != BRK_METHOD_ROM) continue;
	if ((addr&omsk) != (brkList[i].addr&omsk)) continue; /* not same line */
	if ((addr&~tmsk) == (brkList[i].addr&~tmsk)) return(0); /* same tag */
	}
return(1);
}

/*************************************************************
*/
void setFlushneeded_401x(Ulong addr,int size)
{
if (is_ocm(addr)) ; /* 980225 */
else {
	printDiag(1,"iflush & dflush needed\n");
	if (icache_size != 0) iflush_needed += size;
	if (dcache_size != 0) dflush_needed += size;
	}
}


/*************************************************************
*  void brkInstall_401x(type)
*	type=1 install regular+temp bpts
*	type=2 install trace bpts
*/
void brkInstall_401x(int type)
{
int i,flag;
Ulong dcs,addr;
OcmRec *p;

printDiag(1,"brkInstall_401x(%d)\n",type);
flag = 0;
send_buffer();
for (i=0;i<MAX_BPT;i++) {
	/* first discard the entries we aren't going to handle */
	if (brkList[i].type==0) continue;
	if (type == 1 && brkList[i].type == BPTYPE_TRACE) continue;
	if (type == 2 && brkList[i].type != BPTYPE_TRACE) continue;

	addr = brkList[i].addr;
	switch (brkList[i].method) {
	    case BRK_METHOD_RAM :
		printDiag(1,"installing ram bpt at %08x\n",addr);
		if ((p=is_ocm(addr)) && p->func) {
			brkList[i].val = run_ocm(p,0,addr,4,0);
			run_ocm(p,1,addr,4,BPT_CODE);
			}
		else {
			brkList[i].val = read_target(XT_MEM,addr,4);
			/* write_target(XT_MEM,addr,BPT_CODE,4); */
			printDiag(1,"sw %08x->%08x\n",BPT_CODE,addr);
			writeGpr(8,BPT_CODE);
			writeGpr(9,addr);
			send_instr(SW(8,0,9));
			readA0();
			setFlushneeded(addr,4);
			}
		brkList[i].isset = 1;
		break;

	    case BRK_METHOD_ROM :
		printDiag(1,"installing rom bpt at %08x\n",addr);
		if (!flag) flush_target(ICACHE);
		flag = 1;
		if (!(readCache_401x(1,ICACHETAG,addr)&VALID_BIT))
			setupcacheline_401x(addr);
		wrwdtocache_401x(addr,BPT_CODE);
		brkList[i].isset = 1;
		break;

	    case BRK_METHOD_HW :
		if (brkList[i].type == BPTYPE_DATA) {
			printDiag(1,"installing hwdb bpt at %08x\n",addr);
			writeGpr(8,addr);
			send_instr(MTC0(8,DBX_BDA));
			writeGpr(8,brkList[i].mask);
			send_instr(MTC0(8,DBX_BDAM));
			send_instr(0);
			send_instr(MFC0(4,DBX_DCS));
			send_instr(0);
			dcs = readA0();
			dcs |= DCS_TR|DCS_UD|DCS_KD|DCS_DE|DCS_DAE;
			if (brkList[i].aux[0]&2) dcs |= DCS_DR;
			if (brkList[i].aux[0]&1) dcs |= DCS_DW;
			}
		else {
			printDiag(1,"installing hwib bpt at %08x\n",addr);
			writeGpr(8,addr);
			send_instr(MTC0(8,DBX_BPC));
			writeGpr(8,brkList[i].mask);
			send_instr(MTC0(8,DBX_BPCM));
			send_instr(0);
			send_instr(MFC0(4,DBX_DCS));
			send_instr(0);
			dcs = readA0();
			dcs |= DCS_TR|DCS_UD|DCS_KD|DCS_DE|DCS_PCE;
			}
		writeGpr(8,dcs);
		send_instr(MTC0(8,DBX_DCS));
		readA0();
		brkList[i].isset = 1;
		break;
	    default : 
		printDiag(0,"%d: error bad method\n",brkList[i].method);
		return;
	    }
	}
}

/*************************************************************
*  int brkRemove_401x(epc)
*	returns type: 0=none 1=bpc 2=bda 3=itemp 4=sstep
*/
int brkRemove_401x(Ulong epc)
{
int i,type,flag;
Ulong ccc;
OcmRec *p;

printDiag(1,"brkRemove_401x(%08x)\n",epc);
send_buffer();
type = flag = 0;
for (i=0;i<MAX_BPT;i++) {
	/* first discard the entries we aren't going to handle */
	if (brkList[i].type==0) continue;
	if (brkList[i].isset==0) continue;

	if (epc == brkList[i].addr) type = brkList[i].type;
	switch (brkList[i].method) {
	    case BRK_METHOD_RAM :
		if ((p=is_ocm(brkList[i].addr)) && p->func) {
			run_ocm(p,1,brkList[i].addr,4,brkList[i].val);
			}
		else {
			printDiag(1,"sw %08x->%08x\n",
				brkList[i].val,brkList[i].addr);
			writeGpr(8,brkList[i].val);
			writeGpr(9,brkList[i].addr);
			send_instr(SW(8,0,9));
			readA0();
			setFlushneeded(brkList[i].addr,4);
			}
		brkList[i].isset = 0;
		break;

	    case BRK_METHOD_ROM :
		ccc = read_target(XT_CP0,C0_CCC,0);
		writeGpr(8,ccc&~CCC_ISR1);
		send_instr(MTC0(8,C0_CCC));
		readA0();
		brkList[i].isset = 0;
		setFlushneeded(brkList[i].addr,4);
		break;

	    case BRK_METHOD_HW :
		writeGpr(8,0);
		send_instr(MTC0(8,DBX_DCS));
		readA0();
		brkList[i].isset = 0;
		break;
	    }
	if (brkList[i].type == BPTYPE_ITMP) brkList[i].type = 0;
	if (brkList[i].type == BPTYPE_TRACE) brkList[i].type = 0;
	}
return(type);
}