400x.c

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

				}
			}
		}
	else if (n==0) { /* 1st arg is the set# */
		if (!get_rsa(&set,av[i])) return;
		n++;
		}
	else if (n==1) { /* 2nd arg is the addr */
		if (!get_rsa(&adr,av[i])) return;
		n++;
		}
	else if (n==2 && wflag) { /* 3rd arg is the value */
		if (!get_rsa(&val,av[i])) return;
		n++;
		}
	else {
		printf("%s: too many args\n",av[i]);
		return;
		}
	}
if (n==0) set = 0;
if (n<2) adr = next_adr;

adr &= ~(cache_line_size-1); /* force addr to line boundary */

if (wflag) {
	if (tflag && !iflag) cachetag = DCACHETAG;
	else if (tflag && iflag) cachetag = ICACHETAG;
	else if (!tflag && iflag) cachetag = ICACHERAM;
	else if (!tflag && !iflag) cachetag = DCACHERAM;
	writeCache(set,cachetag,adr,val,4);
	return;
	}

if (iflag) {
	cachetag = ICACHETAG;
	msk = (icache_size)-1;
	cache_size = icache_size;
	}
else {
	cachetag = DCACHETAG;
	msk = (dcache_size)-1;
	cache_size = dcache_size;
	}


printf("Displaying %s set %d\n",(iflag)?"icache":"dcache",set);
for (n=j=0;j<8;adr += cache_line_size,n++) {
	if (n > cache_size/cache_line_size) break;
	tag = readCache_400x(set,cachetag,adr);
	if (vflag && (tag&0xf)==0) continue;
	if (lflag && (tag&0x10)==0) continue;
	printf("%08x  ",adr);
	if (iflag) {
		printf("%08x ",readCache_400x(set,ICACHERAM,adr));
		printf("%08x ",readCache_400x(set,ICACHERAM,adr+4));
		printf("%08x ",readCache_400x(set,ICACHERAM,adr+8));
		printf("%08x ",readCache_400x(set,ICACHERAM,adr+12));
		}
	else {
		dadr = K0BASE|(tag&~msk)|(adr&msk);

		/* 970225 you can only display the data if the valid 
		 * bit is set 
		 */
		if (tag&1) printf("%08x ",read_target(XT_MEM,dadr+0,4));
		else printf("xxxxxxxx ");
		if (tag&2) printf("%08x ",read_target(XT_MEM,dadr+4,4));
		else printf("xxxxxxxx ");
		if (tag&4) printf("%08x ",read_target(XT_MEM,dadr+8,4));
		else printf("xxxxxxxx ");
		if (tag&8) printf("%08x ",read_target(XT_MEM,dadr+12,4));
		else printf("xxxxxxxx ");
		}
	printf(" %08x\n",tag);
	j++;
	}
next_adr = adr;
}
#endif

/*************************************************************
*  void brkInstall_400x(type)
*	type=1 install regular+temp bpts
*	type=2 install trace bpts
*/
void brkInstall_400x(type)
int type;
{
int i;
Ulong dcs,addr;
OcmRec *p;

printDiag(1,"\nbrkInstall_400x(%d)\n",type);

for (i=0;i<MAX_BPT;i++) {
	/* first discard the entries we aren't going to handle */
	if (brkList[i].type==0) continue;
	if (type == 1 && brkList[i].type == BPTYPE_TRACE) continue;
	if (type == 2 && brkList[i].type != BPTYPE_TRACE) continue;

	addr = brkList[i].addr;
	switch (brkList[i].method) {
	    case BRK_METHOD_RAM :
		printDiag(1,"installing ram bpt at %08x\n",addr);
                if ((p=is_ocm(addr)) && p->func) {
                        if (addr&1) {
                                addr &= ~1;
                                brkList[i].val = run_ocm(p,0,addr,2,0);
                                run_ocm(p,1,addr,2,TINY_BPT_CODE);
				setFlushneeded(addr,2);
                                }
                        else {
                                brkList[i].val = run_ocm(p,0,addr,4,0);
                                run_ocm(p,1,addr,4,BPT_CODE);
				setFlushneeded(addr,4);
                                }
                        brkList[i].isset = 1;
                        break;
                        }

                if (addr&1) {
                        addr &= ~1;
                        brkList[i].val = read_target(XT_MEM,addr,2);
			writeGpr(8,TINY_BPT_CODE);
			writeGpr(9,addr);
			send_instr(SH(8,0,9));
			setFlushneeded(addr,2);
                        }
                else {
                        brkList[i].val = read_target(XT_MEM,addr,4);
			writeGpr(8,BPT_CODE);
			writeGpr(9,addr);
			send_instr(SW(8,0,9));
			setFlushneeded(addr,4);
                        }
		readA0();
		brkList[i].isset = 1;
		break;

	    case BRK_METHOD_ROM :
		printDiag(1,"installing rom bpt at %08x\n",addr);

                if (addr&1) {
                        addr &= ~1;
			setilockbpt_400x(addr,TINY_BPT_CODE,2);
			}
		else setilockbpt_400x(addr,BPT_CODE,4);

#if 0
Ulong cfg,tag,vmask;
		cfg = read_target(XT_MEM,M_CFG4001,4);
		if ((cfg&CFG_ISIZEMASK) == CFG_ISIZE_8) {
			/* handle the irefillsz=8 case */
			setupcacheline_400x(addr); /* copy mem to cache */
			}

		tag = readCache_400x(0,ICACHETAG,addr);
		vmask = 1<<((addr>>2)&3);
		if (!(tag&LCK_BIT)) {
			tag &= ~0xf;
			tag |= LCK_BIT;
			}
		tag |= vmask;
		writeCache(0,ICACHERAM,addr,BPT_CODE,4);
		writeCache(0,ICACHETAG,addr,tag,4);
		/* make sure that it is not in set1 */
		writeCache(1,ICACHETAG,addr,0,4);	
#endif

		brkList[i].isset = 1;
		break;

	    case BRK_METHOD_HW :
		if (dbx_needs_pa) addr &= 0x1fffffff; /* convert to PA */
		if (brkList[i].type == BPTYPE_DATA) {
			printDiag(1,"installing hwdb bpt at %08x\n",addr);
			writeGpr(8,addr);
			send_instr(MTD(8,DBX_BDA));
			writeGpr(8,brkList[i].mask);
			send_instr(MTD(8,DBX_BDAM));
			send_instr(0);
			send_instr(MFD(4,DBX_DCS));
			send_instr(0);
			dcs = readA0();
			dcs |= DCS_TR|DCS_UD|DCS_KD|DCS_DE|DCS_DAE;
			if (brkList[i].aux[0]&2) dcs |= DCS_DR;
			if (brkList[i].aux[0]&1) dcs |= DCS_DW;
			}
		else {
			printDiag(1,"installing hwib bpt at %08x\n",addr);
			writeGpr(8,addr);
			send_instr(MTD(8,DBX_BPC));
			writeGpr(8,brkList[i].mask);
			send_instr(MTD(8,DBX_BPCM));
			send_instr(0);
			send_instr(MFD(4,DBX_DCS));
			send_instr(0);
			dcs = readA0();
			dcs |= DCS_TR|DCS_UD|DCS_KD|DCS_DE|DCS_PCE;
			}
		writeGpr(8,dcs);
		send_instr(MTD(8,DBX_DCS));
		readA0();
		brkList[i].isset = 1;
		break;
	    default : 
		printDiag(0,"%d: error bad method\n",brkList[i].method);
		return;
	    }
	}
printDiag(1,"\n");
}

/*************************************************************
*  int brkRemove_400x(epc)
*	returns type: 0=none 1=bpc 2=bda 3=itemp 4=sstep
*/
int brkRemove_400x(epc)
Ulong epc;
{
int i,type,cnt;
Ulong addr;
OcmRec *p;

if (nobrkRemove) return(0);
nobrkRemove = 1;

type = cnt = 0;
for (i=0;i<MAX_BPT;i++) {
	/* first discard the entries we aren't going to handle */
	if (brkList[i].type==0) continue;
	if (brkList[i].isset==0) continue;

	if (epc == brkList[i].addr) type = brkList[i].type;
	switch (brkList[i].method) {
	    case BRK_METHOD_RAM :
		addr = brkList[i].addr;
		if (cnt++ == 1) printDiag(1,"\n");
		printDiag(1,"brkRemove_400x: %d ram bpt %08x\n",i,addr);
                if ((p=is_ocm(addr)) && p->func) {
                        if (addr&1) run_ocm(p,1,addr,2,brkList[i].val);
                        else run_ocm(p,1,addr,4,brkList[i].val);
                        break;
                        }
                if (addr&1) {
			writeGpr(8,brkList[i].val);
			writeGpr(9,addr&~1);
			send_instr(SH(8,0,9));
			setFlushneeded(addr,2);
			}
                else {
			writeGpr(8,brkList[i].val);
			writeGpr(9,addr);
			send_instr(SW(8,0,9));
			setFlushneeded(addr,4);
			}
		readA0();
		brkList[i].isset = 0;
		break;

	    case BRK_METHOD_ROM :
		addr = brkList[i].addr;
		if (cnt++ == 1) printDiag(1,"\n");
		printDiag(1,"brkRemove: %d rom bpt %08x\n",i,addr);
		writeCache(0,ICACHETAG,addr,0,4);
		setFlushneeded(addr,4);
#if 0 /* this doesn't work on the 4101 */
		/* handle the irefillsz==8 case */
		cfg = read_target(XT_MEM,M_CFG4001,4);
		if ((cfg&CFG_ISIZEMASK) == CFG_ISIZE_8) {
			if (addr&0x10) writeCache(0,ICACHETAG,addr&~0x10,0,4);
			else writeCache(0,ICACHETAG,addr|0x10,0,4);
			}
#endif
		brkList[i].isset = 0;
		break;

	    case BRK_METHOD_HW :
		if (cnt++ == 1) printDiag(1,"\n");
		printDiag(1,"brkRemove: %d hw bpt\n",i);
		send_instr(MTD(0,DBX_DCS)); /* 980823 */
		readA0();
		brkList[i].isset = 0;
		break;
	    }
	if (brkList[i].type == BPTYPE_ITMP) brkList[i].type = 0;
	if (brkList[i].type == BPTYPE_TRACE) brkList[i].type = 0;
	}
nobrkRemove = 0;
if (cnt) printDiag(1,"\n");
return(type);
}

/*************************************************************
*  void setupcacheline_400x(addr)
*	This routine sets things up for rom bpts when irefill=8wds
*	8 wd refill requires that all 4 valid bits are set
*	Copy real memory bytes to the correct line.
*	Write the correct tag and valid bit.
*/
void setupcacheline_400x(addr)
Ulong addr;
{
Ulong cfg,savedcfg,addrmsk;
int n;

/* 
 * copy data from memory
 * 	operation: 
 *		for (r10=4;r10>0;r10--) *r8++ = *r9++;
 *	r2,r4 = tmp
 *	r5 = addr of cfg reg
 */


savedcfg = cfg = read_target(XT_MEM,M_CFG4001,4);
cfg &= ~(CFG_CMODEMASK|CFG_IS1EN|CFG_DSIZEMASK|CFG_ISIZEMASK);
cfg |= (CFG_ICEN|CFG_DCEN);

writeGpr(8,addr&~(cache_line_size-1));
writeGpr(9,K1BASE|addr&~(cache_line_size-1));
writeGpr(10,cache_line_size/4);	/* number of words to copy */
writeGpr(5,M_CFG4001);

n = 1; /* start of loop */
n += writeGpr(4,savedcfg);
n += send_instr(SW(4,0,5));
/*n += send_instr(LW(0,0,5)); /* wbflush */
n += send_instr(0);
n += send_instr(0);
n += send_instr(0);
n += send_instr(LW(2,0,9));	/* read memory */

n += writeGpr(4,cfg|CFG_CMODE_IDATA); /* data */
n += send_instr(SW(4,0,5));
/*n += send_instr(LW(0,0,5)); /* wbflush */
n += send_instr(0);
n += send_instr(ADDIU(9,9,4));
n += send_instr(SUBIU(10,1));
n += send_instr(SW(2,0,8));	/* write cache entry */
n += send_instr(BNE(10,0,0-n));
n += send_instr(ADDIU(8,8,4));
/* end of loop */

/* write the tag */
n += writeGpr(4,cfg|CFG_CMODE_ITEST); /* tag */
n += send_instr(SW(4,0,5));
/*n += send_instr(LW(0,0,5)); /* wbflush */
n += send_instr(0);
n += writeGpr(9,addr);
addrmsk = (0x7<<29)|(icache_size-1);
n += writeGpr(8,(addr&~addrmsk)|0x1f); /* 0x1f = lock + 4 valid bits */
n += send_instr(SW(8,0,9));

/* restore cfg */
n += writeGpr(4,savedcfg);
n += send_instr(SW(4,0,5));
/*n += send_instr(LW(0,0,5)); /* wbflush */
n += send_instr(0);
n += send_instr(0);
readA0();
}

/*************************************************************
*  ilockReq_400x(addr)
*	verify that other ilock bpts don't conflict with this one
*		(ie. are a cachesize multiple apart).
*	Also verify that lock bit is not already set.
*/
int ilockReq_400x(addr)
Ulong addr;
{
Ulong tag;
#if 0
Ulong tmsk,omsk;
int i;
#endif

if (!has_ilock) return(0);

/* no go if Iset0 is not enabled */
if (!(read_target(XT_MEM,M_CFG4001,4)&CFG_ICEN)) return(0);

tag = readCache_400x(0,ICACHETAG,addr);
if (tag&LCK_BIT) return(0);

#if 0 /* 980319 */
tmsk = (icache_size)-1; /* tag mask */
omsk = tmsk&~(cache_line_size-1);
for (i=0;i<MAX_BPT;i++) {
	if (brkList[i].type==0) continue;
	if (brkList[i].method != BRK_METHOD_ROM) continue;