a65066.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/a65066.s
 * Purpose: Part of C runtime library
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	990212	Created from a90084.s
 */

/* This version is for the hw emulation model. So it uses the old DCAM-103
 * type memory controller rather than the fbus controller that the real chip
 * will use.
 */


#ifndef L65066
#define L65066
#endif
#include <mips.h>

	.globl a65066init
	.ent a65066init
a65066init:
	beq     a0,zero,1f
	j       c65066init
    1:

#ifdef USE_FBUS
 # Setup Bus Unit Chip Selects
 #
 #============ Set up FLASH in addr space assign to CS0 ===================
 #
 #  Note: FACMP0 and FACMP1 are initialized on startup to a 2M space starting
 #  at address 0x1fc00000.   These registers only need to be changed if you
 #  have a boot flash larger than 2 Meg in size.

        li      t1, M_FBUSTA
	li	t2, 0x00161111
        sw      t2, (t1)               # Set FBUSTA = 1 turn around time

        li      t1, M_FACFG0
        li      t0, 0x02949517         # Set 8 bit, 11 wait states     
        sw      t0, (t1)               # Store Flash Timing settings

 #============ Initialize random register       ======================

        .set noreorder
        mtc0    zero, C0_RANDOM        # initialize the random register
        nop     
        .set reorder

 # Initialize SDRAM controller
 #
 # This routine inits the SDRAM controller on the 4102.  It begins by
 # configuring the address range for the SDRAM and all of the timing
 # parameters.  It then waits for 100 usec using the timer0 as a count
 # down.  Finally it issues a precharge to bank 0, 1, 2 & 3 followed by 2
 # refreshes and configures the SDRAM for 1 word burst.

 # The SDRAM controller strobes out a new address with each read request.


	# Set SDRAM clock
        li      t0, M_SCR2        # Set bclkp to run at
                                        # pclk speed
        lw      t2, (t0)                # Read current PLL jumper status
        and     t2, 0x00000010          # Mask off all but the PLL bit
        li      t1, 0x000200a8          # and dclkp to run at
        or      t1, t2                  # bclk or 100MHz
        sw      t1, (t0)                # and enable 4101
                                        # compatibility mode

	# Issue COMMAND INHIBIT by not reading or writing to 
	# DRAM and wait for 100 us

	li      t0, M_TMR4001+O_TIC0
	li      t1, M_TMR4001+O_TCC0

	li      t2, 0x00000100          # Setup Timer to wait 
					# 100us  0x2710
	sw      t2, (t0)                # Store data
	li      t0, M_TMR4001+O_TMODE
	li      t2, 0x00000011          # Enable Timer 0 Disable 
					# Timer 1
	sw      t2, (t0)                # Store in Register

1:
	lw      t2, (t1)                # Read from Counter
	bne     zero, t2, 1b            # Loop till done

	# Enable SDRAM in addr range 2

	li      t0, M_FACMP2		# Set FACMP2
	li      t2, 0x07ff0000          # Address range 2 covers 
					# 0x00000000 to
	sw      t2, (t0)                # 0x00ffffff, 16MB Dram

	# Set SDRAM Configuration

	li      t0, M_FSDRAM
	li      t2, 0x000d8609          # Set SDRAM to 4 banks, 
					# 15.6 usec refresh
	sw      t2, (t0)                # 8 bit page size, 4 Meg 
					# bank size 

	# Enable SDRAM
	li      t0, M_FACFG2
	li      t1, 0xd0000001          # enable SDRAM 32 bit 
					# wide bus         
	sw      t1, (t0)        

	# Set FSDRAMT timing register

	li      t0, M_FSDRAMT     # Set SDRAM Timing for 
					# Lat = 3 cks
	li      t2, 0x0000f0aa          # tRC = 2 cks, tCL = 3 cks, 
					# tRAS = 7 cks
	sw      t2, (t0)                # Set Init Bit so that next 
					# read is a bank 
					# Precharge.  Set for MODE 
					# Register write 
					# on next Write to SDRAM
						
	# Issue a Precharge to each bank of SDRAM
	li      t1, 0xa0000000          # Execute dummy read to 
					# uncached SDRAM
	lw      zero, (t1)              # Read Banks in order to 
					# precharge
 
	# Issue 2 Refresh cycles to SDRAM

	li      t0, M_FSDRAM
	li      t2, 0x000d8609          # Set SDRAM Config

	sw      t2, (t0)                # Store in FSDRAM to cause 
					# a refresh
	lw      zero, (t0)              # Flush write buffers
	ori     t0, t0, 0x0             # Flush write buffers

	sw      t2, (t0)                # Store in FSDRAM to cause 
					# a second refresh    
	lw      zero, (t0)              # Flush write buffers
	ori     t0, t0, 0x0             # Flush write buffers

	# Set SDRAM mode register
	li      t1, 0xa008c000          # Set SDRAM Mode Reg to 
					# Latency of 3
					# and burst of 1, shift 8 
					# bits for row addr
					# shift 2 more for word width
	sw      zero, (t1)              # Execute SDRAM Mode Reg write
					# by reading from a0006000 
					# uncached
        
	li      t0, M_FSDRAMT     	# Disable Mode Register 
					# Write & Init
	li      t1, 0x000038aa          
	sw      t1, (t0)         
#else
	# set BDC    
	# !!!  change so it doesn't change device size ####
	li	t1,M_084_BDC
	li	t0,0x000009d2	# SRAM, 8BIT,DC1=0,DW1=1,EA=0,WS=7,DC=2 
	sw	t0,(t1)

	# set DOC
	li	t1,M_084_D0C
	#li	t0,0x00000897	# DRAM, 32BIT,RCD=2,CPW=0,RP=1,CP=0,EDO=1 
	li	t0,0x00000a2f
	sw	t0,(t1)

	# set D2C
	li	t1,M_084_D2C
	li	t0,0x000009d2	# SRAM, 8BIT,DC1=0,DW1=1,EA=0,WS=7,DC=2 
	sw	t0,(t1)

	# set D3C
	li	t1,M_084_D3C
	li	t0,0x000009d4	# SRAM, 16BIT,DC1=0,DW1=1,EA=0,WS=7,BRE=0,DC=2 
	sw	t0,(t1)

	# set REFRESH
	li	t1,M_084_REFRESH
	li	t0,200		# guess?
	sw	t0,(t1)
#endif

	# set CFG
	li	t1,M_SCR1
	li	t0,(SCR1_IRFLSZ_4|SCR1_DRFLSZ_4|SCR1_DCEN|SCR1_ICEN)
	sw	t0,(t1)

	# enable the clocks
	li	t1,M_084_SYSCLK
	li	t0,(SYSCLK_MCLKENP|SYSCLK_BIUCLK|SYSCLK_TMR0CLK)
	or	t0,(SYSCLK_TMR1CLK|SYSCLK_SIO0CLK|SYSCLK_SIO1CLK)
	or	t0,(SYSCLK_SIO2CLK)
1:	# sw	t0,(t1)			
	#lw	t2,(t1)
	li	t0,0x1ffff
	sw	t0,(t1)

	# select the correct cache flushing routines
	la	s0,r4001_flush

	j	ra
	.end a65066init