a64388.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/a64388.s
 * Purpose: Provide low-level init code for 64388 RAP
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	970827	Created in pmon4
 *	980701	Adapted to PMON5 format
 *	981216	Updated EPROM settings per email from Russell.
 */

#ifndef LR64388
#define LR64388
#endif
#include <mips.h>

	.globl a64388init
	.ent a64388init
a64388init:
	########### RAP Evaluation Board ##############
	beq     a0,zero,1f
	j       c64388init
    1:

	.set noreorder
/*********************************************************************
* Set up the Icache and Dcache data RAMs
*   Enable:	BGE	BIU Bus Grants
*		IE0	Icache Set 0
*		IE1	Icache Set 1	
*		IS8	Icache Set size = 8k
*		DE0	Dcache Set 0
*		DE1	Dcache Set 1
*		DS4	Dcache Set size = 4k
*		MUL	Hardware Multiplier Enable @
*		MAD 	Multiplier Supports Accumulate Extensions (MULT must be set) @
*              CMP     Set R3000 compatibility mode +
*              WB      WriteBack -
*
*		@ = Required for Multiplication
*	        + = Added only if in R3000 compatibility mode
*              - = May be added if desired
********************************************************************/

        move    t0, zero
	li	t0, CCC_BGE | CCC_IE0 | CCC_IE1 | CCC_IS8 | CCC_DE0 | CCC_DE1 | CCC_DS4 | CCC_CMP
#ifndef INCLUDE_MDEM
	or	t0, CCC_MUL | CCC_MAD
#endif

        mtc0    t0, C0_CCC		# load the CP0 configuration register
	nop

	li	t0, 0xB0008A10		# Initialize the RTC Clock
	li	t1, 2
	sw	t1, (t0)		# Reset RTC
	li	t1, 1
	sw	t1, (t0)		# Enable RTC
	li	t0, 80000
1:	subu	t0, 1
	bne	t0, zero, 1b		# Delay to allow RTC clock to stabilize
	nop

        li      t0, 0xB0008160   	# Enable PCI access to RAP registers.
        lw      t1, (t0)
	nop
        or      t1, 0x80
        sw      t1, (t0)

        li      t0,M_RAP_AddrMap	# Skip mem controller initialization
        lw      t0,(t0)			# If executing out of RAM.
        nop
        li      t1,0x600
        bne     t0,t1,flushRap
        nop

/********************************************************************
* SDRAM power up sequence (via Memory Controller)
********************************************************************/

	/****************************************
	* Write Delay Config Register          *
	****************************************/

				# Setup Delay Config Register to:	
				#	Sys/PLL Clock Delay    = 3.5 ns
				#       Read Clock Delay       = 0.0 ns
				#	Write Data Clock Delay = 0.0 ns

				#	SDRAM Clock Delay      = 0.5 ns
	
	li	t0,0x00000e01	# Fill t0 with Delay Config values
	li	t3,0xb0008204	# Delay Config Reg Addr -> t0
	sw	t0,0(t3)	# Set delay Config Register
	
	/*******************************************************************
	* Setup EEPROM, PHY, and SDRAM					   *
	*******************************************************************/
	
eeprom_pup:

       /*********************************************************************
        * EEPROM Configuration (via Memory Controller)
        *********************************************************************/

				# Configure EPROM to:
                                #	Write High Time     [21:20] = 3 cycles
				#	Write Low Time      [19:16] = 7 cycles
				#	Read Recovery Time  [6:4]   = 3 cycle
				#	Read Time           [3:0]   = 7 cycle

	li	t0,0x00370037	# settings -> t0 // 981216 was 00340034
	li	t1,0xb0008228	# EPROM Control Register -> t1
	sw	t0,0(t1)	# Configure EPROM

phy_pup:	

       /*********************************************************************
        * PHY Configuration (via Memory Controller)
        *********************************************************************/

				# Configure PHY to:
				#	Mux                  [31] = 0  disabled
				#	Address Latch Enable [30:27] = 7 cycles
				#	Write High Time      [21:20] = 3 cycles
				#	Write Low Time       [19:16] = 5 cycles
				#	Read Recovery Time   [6:4] = 6 cycles
				#	Read Time            [3:0] = 10 cycles

	li	t0,0x3835006a	# Settings -> t0
/*	li	t0,0x78340034	#  old settings for 40 MHz operation */
	li	t1,0xb0008230	# PHY Control Register -> t1
	sw	t0,0(t1)	# Configure PHY

sdram_pup:	
			
	#################################################################################
	#										#
	# All Rap configurations have a CAS latency of 3, although this should not      #
	# affect performance.  The refresh/active command period was determined from    #
	# the value specified by trc in the NEC Dynamic RAMs Data Book (pg 1049).       #
	#										#
	#										#
	# The SDRAM should typically be refreshed every 64ms.  In order to calculate	#
	# the number of cycles need between refresh commands, use the following		#
	# equation:									#
	#										#
	#                    (64ms)*(ClockFreq)						#
	#    Num Cycles =  -----------------------					#
	#                  2^(SDRAM Row Addr Bits)					#
	#										#
	################################################################################# 

	/********************************************
	* Get clock frequency                      *
	********************************************/

#ifdef CLKFREQ

	li	s0, CLKFREQ*1000000

#else

	move	t9, ra		# save away return address
	jal	getRAPClkFreq	# getRAPClkFreq must not use t9
	nop			# returns with clk freq in v0
	move	ra, t9		# restore return address
	move	s0, v0		# place clk freq in s0

#endif  /* CLKFREQ */

	/********************************************
	* Set variables for determining clock freq *
	********************************************/

#if 0
	li	s1,   2000000
#endif
	li	s2,  34000000
	li	s3,  67000000
	li	s4, 101000000


#if 0
	/************************************
	* Are we at 1MHz or in 1MHz range? *
	************************************/

	bgt	s0, s1, 1f	# If not at 1 MHz or in 1 MHz range, jump forward
	nop

				# If 1 MHz operation
				# Set the SDRAM Control Reg to:
				#	LP   = OFF
				#	CL   = 3
				#       RC   = 2
				#       DP2  = 0
				#       RBS  = 1
	                        #	BBD2 = 0
				# Set refresh rate to: 16 cycles

	li	t1,0x00302100	# Fill t1 with SDRAM control
	li	t2,0x00000010	# Fill t2 with refresh rate (for 614400 Hz)
	b	4f		#  Branch used instead of jump since it
	nop			#  only has a 16 bit offset
#endif

	/**************************************
	* Are we at 33MHz or in 33MHz range? *
	**************************************/

1:	bgt	s0, s2, 2f	# If not at 33 MHz or in 33 MHz range, jump forward
	nop

				# If 33 MHz operation (Test Chip)
				# Set the SDRAM Control Reg to:
				#	LP   = OFF
				#	CL   = 3
				#       RC   = 4
				#       DP2  = 0
				#       RBS  = 1
	                        #	BBD2 = 0
				# Set refresh rate to: 625 cycles

	li	t1,0x00304100	# Fill t1 with SDRAM control
	li	t2,0x00000204	# Fill t2 with refresh rate
	b	4f		#  Branch used instead of jump since it
	nop			#  only has a 16 bit offset

	/**************************************
	* Are we at 40MHz or in 66MHz range? *
	**************************************/

2:	bgt	s0, s3, 3f	# If not at 40 MHz or in 66 MHz range, jump forward
	nop

				# If 40 MHz operation (Test Chip)
				# Set the SDRAM Control Reg to:
				#	LP   = OFF
				#	CL   = 3
				#       RC   = 7
				#       DP2  = 0
				#       RBS  = 1
	                        #	BBD2 = 0
				# Set refresh rate to: 625 cycles

	li	t1,0x00307100	# Fill t1 with SDRAM control
	li	t2,0x00000271	# Fill t2 with refresh rate
	b	4f		#  Branch used instead of jump since it
	nop			#  only has a 16 bit offset

	/******************************************
	* We must be at 80MHz or in 100MHz range *
	******************************************/

				# Must be at 80 MHz or in 100 MHz range
				# Set the SDRAM Control Reg to:
				#	LP   = OFF
				#	CL   = 3
				#       RC   = 10
				#       DP2  = 0
				#       RBS  = 1
	                        #	BBD2 = 0
				# Set refresh rate to: 1250 cycles

3:	li	t1,0x0030a100	# Fill t1 with SDRAM control
	li	t2,0x000004e2	# Fill t2 with refresh rate

	/****************************************
	* Write SDRAM control in Mem Controler *
	****************************************/

4:	li	t3,0xb0008208	# SDRAM Control Reg Addr -> t1
	sw	t1,0(t3)	# Store preferences -> SDRAM Control Reg
	
				# Precharge the SDRAM	
	li	t1,0x00000001	# 0x1 -> t0
	li	t3,0xb0008210	# Precharge Cmd Reg Addr -> t1
	sw	t1,0(t3)	# Do a precharge

	/***************************************
	* Write refresh rate to Mem Controler *
	***************************************/
	
	li	t3,0xb0008200	# SDRAM Refresh Reg Addr -> t1
	sw	t2,0(t3)	# Set refresh rate

	/*********************************************************************
	* Have Mem Controler configure SDRAM to agree with above parameters *
	*********************************************************************/
	

				# Set the Mode Reg to:
				#	Burst Length = 8
				#	Wrap Type	= 0
				#	Latency Mode	= 3
	li	t0,0x00000033	# t0 <- 0x33 
	li	t1,0xb0008218	# SDRAM Mode Set Reg -> t1
	sw	t0,0(t1)	# Set Mode Reg (really doesn't matter what this value is)

				# Refer to tech spec info on Mem Controller and NEC
				#  SDRAM part uPD4516821
	li	t0,0x00000033	# t0 <- 0x33
	li	t1,0xa0019800	# You must write to this addr in order to set the Mode reg to 0x33
	sw	t0,0(t1)	# Set Mode Reg

	/**********************************
	* Refresh all SDRAM banks twice  *         
	**********************************/
	
				# Do first refresh of SDRAM
	li	t0,0x00000001	# t0 <- 0x1
	li	t1,0xb0008220	# SDRAM Refresh Cycle Cmd Reg Addr -> t1
	sw	t0,0(t1)	# Refresh SDRAM

				# Do second refresh of SDRAM
				#  Note: must read value first to clear write back buffer
	lw	t3,0(t1)	# SDRAM Refresh Cycle Cmd Reg -> t3
	li	t0,0x00000002	# t0 <- 0x2
	sw	t0,0(t1)	# Refresh SDRAM

       /*********************************************************************
        * Setup Cache Flushing Routines
        *********************************************************************/
flushRap:	

	la	s0,r4010_flush	# select the correct cache flushing routines

       /*********************************************************************
        * Exit RAP Initialization Section
        *********************************************************************/

	.set reorder
	j	ra
	.end a64388init

	.globl getRAPClkFreq
	.ent getRAPClkFreq
getRAPClkFreq:
	.set noreorder

	/********************************************
	 * Initialize the RTC clock                 *
	 ********************************************/	
	li	t0, 0xb0008a10		# RTC Control Register
	li	t1, 0x00000001
	sw	t1, (t0)		# enable RTC

	/********************************************
	 * Loop until RTC clock decrements          *
	 ********************************************/
	li	t0, 0xb0008a00		# RTC Register
	lw	t2, (t0)		# Load RTC Register
	nop
1:	lw	t1, (t0)		# Load RTC Register
	nop
	beq	t1, t2, 1b		# branch back if no change
	nop

	/********************************************
	 * Get number of cycles for RTC decrement   *
	 ********************************************/
	mfc0	t4, C0_COUNT		# Load current count value
	nop
	nop
	nop
	nop
1:	lw	t2, (t0)		# Load RTC Register
	nop
	beq	t1, t2, 1b		# branch back if no change
	nop
	mfc0	t5, C0_COUNT		# Load current count value
	nop
	nop
	nop
	nop

	/********************************************
	 * Calculate frequency                      *
	 ********************************************/
	subu	v0, t5, t4		# Get count difference
	sll	v0, v0, 8		# Multiply by 256 to get clk freq

	/****************************
	 * Return to caller routine *
	 ****************************/
	j	ra
	nop

	.set reorder
	.end getRAPClkFreq