a4101.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/a4101.s
 * Purpose: Part of C runtime library
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	970523	Created from a4003.s
 *	970709	Added wrrombpt4101 as fix for irefill=8 case
 *	970908	Removed excess nop from read CFG
 */

#ifndef LR4101
#define LR4101
#endif
#include <mips.h>

	.globl a4101init
	.ent a4101init
a4101init:
	beq     a0,zero,1f
	j       c4101init
    1:

	# set M_CFG4001
	# wben, ~tlben, ~dberr, pgsz=111, rdpri, cmode=00, dcen, is1en, icen
	# isize=int5,int4 dsize=int3,int2 
	li	t0,(CFG_WBEN|CFG_DCEN|CFG_IS1EN|CFG_ICEN)
	or	t0,(CFG_PGSZ_2K|CFG_CMODE_NORM|CFG_DSNOOP|CFG_ISNOOP)

	# setting of DBS0/1 and IBS0/1 is controlled by jumpers on the
	# board that are connected to the CpCond inputs. But rather than
	# use a whole bunch of bc1t instructions to test them. I connect
	# them to the interrupt inputs and then test the CAUSE register.

	# connect CpCond inputs to interrupt inputs
	or	t0,(CFG_CPC0EN|CFG_CPC1EN|CFG_CPC2EN|CFG_CPC3EN)
	li      t1,M_CFG4001
	sw      t0,(t1)		# write CFG4001
	lw      zero,(t1)	# flush wb

	.set noreorder
	# allow time for CFG change to take effect
	nop
	nop
	mfc0	t1,C0_CAUSE
	nop
	.set reorder
	and	t2,t1,(CAUSE_INT5|CAUSE_INT4)
	srl	t2,14-2
	or	t0,t2
	and	t2,t1,(CAUSE_INT3|CAUSE_INT2)
	srl	t2,12-5
	or	t0,t2
	li	t1,M_CFG4001
	sw	t0,(t1)

        # disconnect cpCond inputs from interrupt inputs
	and     t0,~(CFG_CPC0EN|CFG_CPC1EN|CFG_CPC2EN|CFG_CPC3EN)
	li      t1,M_CFG4001
	sw      t0,(t1)		# write CFG4001
	lw      zero,(t1)	# flush wb

	# set refresh timer (timer0)
	# 60MHz clock 16ms/1024 = 941
	li	t1,M_TMR4001
	li	t0,941
	sw	t0,O_TIC0(t1)
	li	t0,(TMODE_EN0|TMODE_PULSE0)
	sw	t0,O_TMODE(t1)
	lw	zero,O_TMODE(t1)	# flush wb

#if 0
	# enable int0 for berr signals
	.set noreorder
	mfc0	t0,C0_SR
	nop
	or	t0,(SR_IBIT3|SR_IEC)
	mtc0	t0,C0_SR
	nop		# give it time...
	nop
	nop
	.set reorder
#endif

	# select the correct cache flushing routines
	la	s0,r4001_flush

	j	ra
	.end a4101init

/*************************************************************
*  wrrombp4101(Ulong addr)
*	This is only used for rom bpts when irefill=8
*	Copy real memory bytes to the correct line.
*	Write the correct tag and valid bit.
*	Added 970709
*/
	.globl wrrombp4101
	.ent wrrombp4101
wrrombp4101:
	# switch to kseg1
	la	t0,1f
	or	t0,K1BASE
	j	t0
   1:
	# disable ints
	.set noreorder
	mfc0	t8,C0_SR
	nop
	and	t0,t8,~SR_IEC
	mtc0	t0,C0_SR
	nop
	.set reorder

	# read CFG
	li	t5,M_CFG4001
	lw	t7,(t5)
	and	t6,t7,~(CFG_CMODEMASK|CFG_IS1EN|CFG_DSIZEMASK|CFG_ISIZEMASK)
	or	t6,(CFG_ICEN|CFG_DCEN)
	# t6=cfg t7=savedcfg

	# setup for loop
	move	t2,a0
	and	t2,~0xf		# cache_line_size-1
	move	t3,t2
	or	t3,K1BASE
	li	t4,4		# number of words to copy
   1:
	sw	t7,(t5)		# CFG = savedcfg
	.set noreorder
	nop; nop; nop
	.set reorder
	lw	v0,(t3)		# read memory

	move	t0,t6		# cfg
	or	t0,CFG_CMODE_IDATA
	sw	t0,(t5)
	.set noreorder
	nop; nop; nop
	.set reorder
	addu	t3,4
	subu	t4,1
	sw	v0,(t2)		# write cache entry
	addu	t2,4
	bne	t4,zero,1b

	# write the tag
	move	t0,t6		# cfg
	or	t0,CFG_CMODE_ITEST
	sw	t0,(t5)
	.set noreorder
	nop; nop; nop
	.set reorder
	
	# addrmsk = (0x7<<29)|((8*1024)-1);
	# (addr&~addrmsk)|VALID_BIT;
	and	t2,a0,~((0x7<<29)|((8*1024)-1))
	or	t2,0x1f		# lock + 4 valid bits
	sw	t2,(a0)

	# write the breakpoint
	move	t0,t6		# cfg
	or	t0,CFG_CMODE_IDATA
	sw	t0,(t5)
	.set noreorder
	nop; nop; nop
	.set reorder

	li	t0,0x0000000d	# bptcode
	sw	t0,(a0)		# write the value

	# restore CFG
	sw	t7,(t5)
	.set noreorder
	nop; nop; nop
	
	# restore SR
	mtc0	t8,C0_SR
	nop
	nop
	.set reorder

	j	ra
	.end wrrombp4101