f90084.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/f90084.s
 * Purpose: Flush routines for L9A0084
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	980416	Created from r4001cfl.s
 *	980611	Renamed for Tasking tools (8.3 max).
 *	980726	nops removed from reorder sections.
 */

#include <mips.h>
#ifdef L9A0084

/*************************************************************
*  r90084_flush(type,adr)
*	Flush the designated LR90084 cache.
*	Note that this isn't a real subroutine, it just transfers
*	control to the appropriate flush routine.
*	Since the 90084 doesn't have icache locking, there is no
*	difference between cold and warm flush.
*/
	.globl r90084_flush
	.ent r90084_flush
r90084_flush:
	bne	a0,ICACHEI,1f
	j	r90084_iflush

1:	bne	a0,ICACHE,1f
	j	r90084_iflush

1:	bne	a0,DCACHE,1f
	j	r90084_dflush

1:	bne	a0,DCACHEI,1f
	j	r90084_dflush

1:	move	a0,a1
	j	r90084_iaflush
	.end r90084_flush



/*************************************************************
*  r90084_iflush()
*/
	.globl r90084_iflush
	.ent r90084_iflush
r90084_iflush:
	.set	noreorder
	li	t4,8192			# icache_size
	mfc0	t7, C0_SR		# save SR
	nop
	and	t0, t7, ~SR_IEC		# disable interrupts
	mtc0	t0, C0_SR
        
	la	t3, M_084_CCS
	lw	t8, 0(t3)		# save config. register
	nop

	li	t0, K0BASE
	addu	t4, t4, t0		# end of I-cache

	move	t5, t0
	li	t6, 4*4

	.set 	reorder
	la	t0, 1f			# switch to Kseg1
	li	t1, K1BASE
	or	t0, t1
	j	t0
1:
		# flush I-cache
	and	t0, t8,~(CCS_CMODEMASK)
	or	t0, (CCS_DCEN | CCS_ICEN)
	or	t0, CCS_CMODE_ITEST	# I-cache enable
					# D-cache enable
					# I-cache software test
	sw	t0, (t3)
	lw	t0, (t3)
	addu	t0, 1

	move	t0, t5
1:	sw	zero, (t0)
	addu	t0, t6
	bltu	t0, t4, 1b
        
        # restore status and config. register
	.set	noreorder
	sw	t8, (t3)		# restore config. register
	lw	t8, (t3)
        nop
	addu	t8, 1
	mtc0	t7, C0_SR		# restore SR
	j	ra
	nop
	.set	reorder
	.end r90084_iflush

/*************************************************************
*  r90084_dflush()
*	Flush the LR90084 Data cache.
*/
	.globl r90084_dflush
	.ent r90084_dflush
r90084_dflush:
	.set	noreorder
	li	t4,8192			# dcache_size
	mfc0	t7, C0_SR		# save SR
	nop
	and	t0, t7, ~SR_IEC		# disable interrupts
	mtc0	t0, C0_SR

	la	t3, M_084_CCS
	lw	t8, 0(t3)		# save config. register
	nop
        
        la	t0, K0BASE
	addu	t4, t4, t0		# end of D-cache

	move	t5, t0
	li	t6, 4*4

	.set	reorder
	la	t0, 1f			# switch to Kseg1
	li	t1, K1BASE
	or	t0, t1
	j	t0
1:
			
	# flush D-cache
	and	t0, t8,~(CCS_CMODEMASK | CCS_ICEN)
	or	t0, CCS_DCEN
	or	t0, CCS_CMODE_DTEST
					# D-cache enable, I-cache enable
					# D-cache software test
	sw	t0, (t3)			
	lw	t0, (t3)
	addu	t0, 1			

	move	t0, t5
1:	sw	zero, (t0)		
	addu	t0, t6
	bltu	t0, t4, 1b

	# restore status and config. register
	.set	noreorder
	sw	t8, (t3)		# restore config. register
	lw	t8, (t3)
        nop
	addu	t8, 1	
	mtc0	t7, C0_SR		# restore SR
	j	ra
	nop
	.set	reorder
	.end r90084_dflush

/*************************************************************
*  r90084_iaflush(addr)
*	Flush a single entry in the LR90084 Instruction cache.
*/
	.globl r90084_iaflush
	.ent r90084_iaflush
r90084_iaflush:
	# a0=addr
	# return if the address is non cacheable
	srl	t0,a0,29
	bne	t0,5,1f
	j	ra

   1:	# word align the address
	li	t0,~3
	and	a0,t0

	# disable ints
	.set noreorder
	mfc0	t7,C0_SR
	nop
	and	t0,t7,~SR_IEC
	mtc0	t0,C0_SR
	.set reorder

	# switch to Kseg1
	la	t0,1f
	li	t1,K1BASE
	or	t0,t1
	j	t0

1:	lw	t8,M_084_CCS

	and	t0,t8,~(CCS_CMODEMASK|CCS_DCEN)
	or	t0,(CCS_ICEN|CCS_DCEN|CCS_CMODE_ITEST)
	# DCEN has to be on for all software tests     JFK 12/7/95
	sw	t0,M_084_CCS
	lw	t0,M_084_CCS	# wb flush
	addu	t0,1		# wb flush
	.set noreorder;nop;nop;nop;.set reorder

	sw	zero,(a0)

	.set noreorder
	nop
	nop
	nop
	sw	t8,M_084_CCS	# restore CFGREG
	lw	t0,M_084_CCS	# wb flush
	nop
	addu	t0,1		# wb flush
	nop
	mtc0	t7,C0_SR	# restore SR
	.set reorder
	j	ra
	.end r90084_iaflush

#else /* some versions of BSO tools don't like empty files */
	.globl r90084_dummy
	.ent r90084_dummy
r90084_dummy:
	j	ra
	.end r90084_dummy
#endif /* LR90084 */