a4003.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/a4003.s
 * Purpose: Part of C runtime library
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	970402	Created from a4001.s
 */

#ifndef LR4002
#define LR4002
#endif
#include <mips.h>

	.globl a4003init
	.ent a4003init
a4003init:
	beq     a0,zero,1f
	j       c4003init
    1:

	# set M_CFG4001
	# wben, ~tlben, ~dberr, pgsz=111, rdpri, cmode=00, dcen, is1en, icen
	# isize=int5,int4 dsize=int3,int2 
	li	t0,(CFG_WBEN|CFG_DCEN|CFG_IS1EN|CFG_ICEN)
	or	t0,(CFG_PGSZ_2K|CFG_CMODE_NORM|CFG_DSNOOP|CFG_ISNOOP)

	# setting of DBS0/1 and IBS0/1 is controlled by jumpers on the
	# board that are connected to the CpCond inputs. But rather than
	# use a whole bunch of bc1t instructions to test them. I connect
	# them to the interrupt inputs and then test the CAUSE register.

	# connect CpCond inputs to interrupt inputs
	or	t0,(CFG_CPC0EN|CFG_CPC1EN|CFG_CPC2EN|CFG_CPC3EN)
	li      t1,M_CFG4001
	sw      t0,(t1)		# write CFG4001
	lw      zero,(t1)	# flush wb

	.set noreorder
	# allow time for CFG change to take effect
	nop
	nop
	mfc0	t1,C0_CAUSE
	nop
	.set reorder
	and	t2,t1,(CAUSE_INT5|CAUSE_INT4)
	srl	t2,14-2
	or	t0,t2
	and	t2,t1,(CAUSE_INT3|CAUSE_INT2)
	srl	t2,12-5
	or	t0,t2
	li	t1,M_CFG4001
	sw	t0,(t1)

        # disconnect cpCond inputs from interrupt inputs
	and     t0,~(CFG_CPC0EN|CFG_CPC1EN|CFG_CPC2EN|CFG_CPC3EN)
	li      t1,M_CFG4001
	sw      t0,(t1)		# write CFG4001
	lw      zero,(t1)	# flush wb

	# set refresh timer (timer0)
	# 60MHz clock 16ms/1024 = 941
	li	t1,M_TMR4001
	li	t0,941
	sw	t0,O_TIC0(t1)
	li	t0,(TMODE_EN0|TMODE_PULSE0)
	sw	t0,O_TMODE(t1)
	lw	zero,O_TMODE(t1)	# flush wb

#if 0
	# enable int0 for berr signals
	.set noreorder
	mfc0	t0,C0_SR
	nop
	or	t0,(SR_IBIT3|SR_IEC)
	mtc0	t0,C0_SR
	nop		# give it time...
	nop
	nop
	.set reorder
#endif

	# select the correct cache flushing routines
	la	s0,r4001_flush

	j	ra
	.end a4003init