k4102.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

	.set noreorder
	nop
	nop
	nop
	.set reorder
	# Reset s0 to point to start of INSTR_BUFFER.
	li	s0,INSTR_BUFFER
	jal	s0		# execute INSTR_BUFFER
	bal	put_word	# send A0
	b	ice_loop

   1:	# check for RUN_MODE
	li	a2,RUN_MODE
	bne	a2,v0,1f

restore_rfe:
	# It is RUN_MODE. Transfer control to the client.
	# restore regs
	la	k0,SAVEAREA
	lw	AT,ICE_AT*4(k0)
	lw	v0,ICE_V0*4(k0)
	lw	a0,ICE_A0*4(k0)
	lw	a1,ICE_A1*4(k0)
	lw	a2,ICE_A2*4(k0)
	lw	a3,ICE_A3*4(k0)
	lw	t0,ICE_T0*4(k0)
	lw	t1,ICE_T1*4(k0)
	lw	t2,ICE_T2*4(k0)
	lw	t3,ICE_T3*4(k0)
	lw	t4,ICE_T4*4(k0)
	lw	s0,ICE_S0*4(k0)
	lw	ra,ICE_RA*4(k0)
	.set noreorder
	lw	k0,ICE_EPC*4(k0)
	nop
	j	k0		# jump to client
	rfe
	.set reorder

   1:	# check for SENDSAP
	li	a2,SENDSAP
	bne	a2,v0,1f

	# It is SENDSAP. Send address of SAVEAREA.
	la	a0,SAVEAREA
	or	a0,1		# indicate new format
	bal	put_word
	b	ice_loop

   1:	# else. Not a special word.
	sw	v0,(s0)		# save word in INSTR_BUFFER
	addu	s0,4		# ready for next word
	b	ice_loop
	.end ice_loop

	.set at

/*************************************************************
*  get_cmd()
*	Get one word from the serial interface. The result goes
*	in v0.
*/
	.globl get_cmd
	.ent get_cmd
get_cmd:
	li	a2,UART_BASE
	li	a1,4			# get 4 bytes

	# wait for rxrdy
   3:   lw      k0,UART_RXS(a2)
	and	k0,RXS_RXRDY
        beq     k0,zero,3b

	# get the byte
        lw      k0,UART_RXHR(a2)

	# first byte?
	bne	a1,4,2f			# brif not first byte

	# is the byte a wakeup?
	bne	k0,ATTN,2f		# brif not a wakeup

	# wait for txrdy
   1:   lw      k0,UART_TXS(a2)
	and	k0,TXS_TXRDY
        beq     k0,zero,1b

	# send an ack
	li	k0,ACK
        sw      k0,UART_TXHR(a2)
	b	3b

   2:	sll	v0,8			# move word into position
	or	v0,k0			# merge byte with word
	subu	a1,1			# bytecount--
	bne	a1,zero,3b		# do next byte

	j	ra
	.end get_cmd

/*************************************************************
*  get_word()
*       Get one word from the serial interface. The result goes
*       in v0.
*/
        .globl get_word
        .ent get_word
get_word:
        li      a2,UART_BASE
        li      a1,4

   1:   lw      k0,UART_RXS(a2)
	and	k0,RXS_RXRDY
        beq     k0,zero,1b

        lw      k0,UART_RXHR(a2)
        sll     v0,8
        or      v0,k0
        subu    a1,1
        bne     a1,zero,1b

        j       ra
        .end get_word

/*************************************************************
*  put_word()
*       Put one word to the serial interface. The word to be sent
*       comes from a0.
*/
        .globl put_word
        .ent put_word
put_word:
        li      a2,UART_BASE
        li      a1,4

   1:   lw      k0,UART_TXS(a2)
	and	k0,TXS_TXRDY
        beq     k0,zero,1b

        sw      a0,UART_TXHR(a2)
        srl     a0,8
        subu    a1,1
        bne     a1,zero,1b

        j       ra
        .end put_word

/*************************************************************
* 		End of interrupt-level code		     *
*************************************************************/
	.set at


/*************************************************************
*  cpu_init()
*	This is where the CPU-specific init code lives.
*	This implementation is for the bdmr4102 (4102 eval board).
*	This example is designed to use the SerialICE port for connection
*	to the IceController.
*/
	.globl cpu_init
	.ent cpu_init
cpu_init:


 # ============ Set up FLASH in addr space assign to CS0 ===================
 #
 # Note: FACMP0 and FACMP1 are initialized on startup to a 2M space starting
 # at address 0x1fc00000.   These registers only need to be changed if you
 # have a boot flash larger than 2 Meg in size.

        li      t1, M_FBUSTA
	li	t2, 0x00160111	       # 990317
        sw      t2, (t1)               # Set FBUSTA = 1 turn around time

        li      t1, M_FACFG0
        li      t0, 0x02949517         # Set 8 bit, 11 wait states     
        sw      t0, (t1)               # Store Flash Timing settings

 # ============ Setup SRAM in addr space assign to CS3    ==================

        li      t1, M_FACMP3     # Assign CS3 to SRAM in address range
#ifdef BOOT_SRAM
        li      t0, 0x00010000         # 0x00000000 to 0x0001ffff
#else
        li      t0, 0x00010e00         # 0x0e000000 to 0x0e01ffff
#endif
        sw      t0, (t1)               # Assign CS3 address range

        li      t1, M_FACFG3     
        li      t0, 0xc2100005         # 990317 Set 32 bit, 2 wait states
        sw      t0, (t1)               # Store SRAM timing settings
        lw      zero, (t1)

 # Setup BBCC System Configuration Register 
 #
 # Initialize Bus Unit interface.  This routine enables all caches.

#ifdef MIPSEB
                li      s1, M_SCR1        
                li      s0, 0x300010db   # Enable Caches,
					 # snooping, turn off TLB
                sw      s0, (s1)         # Configure SCR1, pg size = 256
#else /* LE needs refill sizes set to 1 */
                li      s1, M_SCR1        
                li      s0, 0x30001093   # Enable Caches,
					 # snooping, turn off TLB
                sw      s0, (s1)         # Configure SCR1, pg size = 256
#endif
                                
#ifndef NO_SDRAM
 # Initialize SDRAM controller
 #
 # This routine inits the SDRAM controller on the 4102.  It begins by
 # configuring the address range for the SDRAM and all of the timing
 # parameters.  It then waits for 100 usec using the timer0 as a count
 # down.  Finally it issues a precharge to bank 0, 1, 2 & 3 followed by 2
 # refreshes and configures the SDRAM for 1 word burst.

 # The SDRAM controller strobes out a new address with each read request.

 # The SDRAM must start on a 32MB boundary.


	# Set SDRAM clock
	li      s0, M_SCR2        # Set bclkp to run at 
					# pclk speed
	lw	s2, (s0)		# Read current PLL jumper status
	and	s2, 0x00000010		# Mask off all but the PLL bit
	li      s1, 0x000200a8          # and dclkp to run at 
	or	s1, s2			# bclk or 100MHz 
	sw      s1, (s0)                # and enable 4101 
					# compatibility mode

	# Issue COMMAND INHIBIT by not reading or writing to 
	# DRAM and wait for 100 us

	li      s0, M_TMR4001+O_TIC0
	li      s1, M_TMR4001+O_TCC0

	li      s2, 0x00000100          # Setup Timer to wait 
					# 100us  0x2710
	sw      s2, (s0)                # Store data
	li      s0, M_TMR4001+O_TMODE
	li      s2, 0x00000011          # Enable Timer 0 Disable 
					# Timer 1
	sw      s2, (s0)                # Store in Register

1:
	lw      s2, (s1)                # Read from Counter
	bne     zero, s2, 1b            # Loop till done

	# Enable SDRAM in addr range 2

	li      s0, M_FACMP2		# Set FACMP2 to 0x00ff0100
#ifdef BOOT_SDRAM
	li      s2, 0x07ff0000          # Address range 2 covers 
					# 0x00000000 to
	sw      s2, (s0)                # 0x00ffffff, 16MB Dram
#else
	li      s2, 0x00ff0200          # Address range 2 covers 
					# 0x02000000 to
	sw      s2, (s0)                # 0x02ffffff, 16MB Dram
#endif

	# Set SDRAM Configuration

	li      s0, M_FSDRAM
	li      s2, 0x000d8609          # Set SDRAM to 4 banks, 
					# 15.6 usec refresh
	sw      s2, (s0)                # 8 bit page size, 4 Meg 
					# bank size 

	# Enable SDRAM
	li      s0, M_FACFG2
	li      s1, 0xd0000001          # enable SDRAM 32 bit 
					# wide bus         
	sw      s1, (s0)        

	# Set FSDRAMT timing register

	li      s0, M_FSDRAMT     # Set SDRAM Timing for 
					# Lat = 3 cks
	li      s2, 0x000057a4          # 990317 tRC = 2 cks, tCL = 3 cks, 
					# tRAS = 7 cks
	sw      s2, (s0)                # Set Init Bit so that next 
					# read is a bank 
					# Precharge.  Set for MODE 
					# Register write 
					# on next Write to SDRAM
						
	# Issue a Precharge to each bank of SDRAM

#ifdef BOOT_SDRAM
	li      s1, 0xa0000000          # Execute dummy read to 
					# uncached SDRAM
#else
	li      s1, 0xa2000000          # Execute dummy read to 
					# uncached SDRAM
#endif
	lw      zero, (s1)              # Read Banks in order to 
					# precharge
 
	# Issue 2 Refresh cycles to SDRAM

	li      s0, M_FSDRAM
	li      s2, 0x000d8609          # Set SDRAM Config

	sw      s2, (s0)                # Store in FSDRAM to cause 
					# a refresh
	lw      zero, (s0)              # Flush write buffers
	ori     s0, s0, 0x0             # Flush write buffers

	sw      s2, (s0)                # Store in FSDRAM to cause 
					# a second refresh    
	lw      zero, (s0)              # Flush write buffers
	ori     s0, s0, 0x0             # Flush write buffers

	# Set SDRAM mode register
	li      t0, M_FSDRAMT
	lw	t4,(t0)
	or	t4,0x8000
	sw	t4,(t0)

#ifdef BOOT_SDRAM
	li      s1, 0xa008c000          # Set SDRAM Mode Reg to 
#else
	li      s1, 0xa208c000          # Set SDRAM Mode Reg to 
#endif

	lb	zero,(s1)
	li      t0, M_FSDRAMT
	and	t4,~0xc000
	sw	t4,(t0)
#endif

#ifndef USE_NO_INTS
	# enable the ICEport's interrupt enable
	li	t0,UART_BASE
	li	t1,RXC_IE
	sw	t1,UART_RXC(t0)
#endif

	 j	ra
	.end cpu_init