k4102.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
* File: lib/k4102.s
* Purpose: A serialICE kernel for the BDMR4102 eval board. This
*	kernel uses the SerialICE-Port interface.
* Author: Phil Bunce ([e-mail])
* Revision History:
*	980615	Created from k4101.s
*	980615	Put data back into bss section, recommend link kseg1. No app.
*	981026	Added changes from email 981025.
*	981028	Moved alt ram addr to a2000000.
*	980130	Removed savearea and instr_buffer from bss.
*	990317	Added mrally's 990315 update
*
* This file contains the PROM resident code (the IceKernel) necessary to
* permit programs to be debugged using LSI Logic's SerialIce.  This
* implementation is for the BDMR4102 (the 4102 evaluation board).
* It uses the ICEport interface to communicate with
* with the ICEmonitor.
*
* The code in this module executes in kseg1 (non cacheable), leaves
* BEV=1, and does not initialize the caches. 
*
* Example compile/link command for this file:
*
*     pmcc -crt0 -prom -syms -T bfc00000 -o k4102 k4102.s
*
* You can either merge your application with this file and include it in
* the PROM, or download your application into RAM and execute it there.
*
* To merge this file with you application. Use the following command line.
*
*     pmcc -prom -board bdmr4102 -o myprog myprog_files...
*
* To download your application into RAM you should compile/link your 
* program using the following command.
*
*     pmcc -board bdmr4102 -o myprog myprog_files...
*
* This file contains the following blocks of code:
*	reset_vector - The start of execution
*	utlb_vector  - UTLB exception handler
*	gen_vector   - Handler for all other exceptions
*	ice_loop     - Main loop of ICE
*	get_cmd      - Get one command word from serial interface
*	get_word     - Get one word from serial interface
*	put_word     - Put one word to serial interface
*	cpu_init     - Perform CPU-specific initialization
*
* This module requires the following areas of RAM:
*	INSTR_BUFFER - This is where the instructions that have been
*		       received from the host are saved.
*	SAVEAREA     - This is where I save the context of the
*		       downloaded program.
*	
*/

/* one and only one of these two lines MUST be enabled */
#define BOOT_SDRAM 	/* SDRAM=0 SRAM=0xa2000000 */
/*#define BOOT_SRAM 	/* SRAM=0 SDRAM=0xa2000000 */

/*#define NO_SDRAM	/* don't enable SDRAM at all. Use w BOOT_SRAM */

/*#define USE_NO_INTS	/* don't use ints for kernel wakeup */

#ifndef LR4102
#define LR4102
#endif

#include <mips.h>

/* Commands that are sent by the IceController */
#define SENDA0		0x12345678	/* execute INSTR_BUFFER */
#define RUN_MODE	0x87654321	/* run application */
#define SENDSAP		0xDEADBEEF	/* send SAVEAREA pointer */
#define ATTN		0x55		/* transfer control to IceKernel */
#define ACK		0xaa		/* reply to ATTN */


/* Offsets into the SAVEAREA */
#define SA_VERS 2
#define ICE_SAV	0	/* save area version */
#define ICE_SAH 1	/* save area header size */
#define ICE_MAP	2	/* bit-map for SAVEAREA */
#define ICE_IBS 3	/* size of instr buffer */
#define ICE_GWP 4	/* pointer to get_word routine */
#define ICE_PWP 5	/* pointer to put_word routine */
#define ICE_EPC	6	/* saved so that it can be set */
#define ICE_LE  7	/* set if little endian */
#define ICE_SAHSIZE 8	/* size of save area header */
/* end of header. The remainder is kernel-specific */
#define ICE_AT	(ICE_SAHSIZE+0)	/* v0 is used to hold the value received */
#define ICE_V0	(ICE_SAHSIZE+1)	/* v0 is used to hold the value received */
#define ICE_A0	(ICE_SAHSIZE+2)	/* a0 is used to hold the value to be sent */
#define ICE_A1	(ICE_SAHSIZE+3)	/* a1 is used as a temp */
#define ICE_A2	(ICE_SAHSIZE+4)	/* a1 is used as a temp */
#define ICE_A3	(ICE_SAHSIZE+5)	/* a1 is used as a temp */
#define ICE_T0	(ICE_SAHSIZE+6)	/* t0 is used by the host as a temp */
#define ICE_T1	(ICE_SAHSIZE+7)	/* t1 is used by the host as a temp */
#define ICE_T2	(ICE_SAHSIZE+8)	/* t2 temp */
#define ICE_T3	(ICE_SAHSIZE+9)	/* t3 temp */
#define ICE_T4	(ICE_SAHSIZE+10)	/* t4 temp */
#define ICE_S0  (ICE_SAHSIZE+11)	/* pointer to INSTR_BUFFER */
#define ICE_RA	(ICE_SAHSIZE+12)	/* ra is needed for bal/jal instrs */
#define ICE_SIZE (ICE_SAHSIZE+13)
#define REG_MAP	0x80011ff6	/* gp regs in SAVEAREA */

/* ICE_MAP is used to tell the driver which of the gp regs have been
 * saved in the SAVEAREA. One bit it used to represent each register,
 * and they must be saved in order. eg. 0x80000000=$31=ra, 
 * 0x00000006=$1&$2=at&v0.
 */

#define UART_BASE 	0xbfff0200
#define UART_RXS	0x0	/* rx status */
#define UART_RXC	0x0	/* rx control */
#define UART_RXHR	0x4	/* rx holding reg */
#define UART_TXS	0x8	/* tx status */
#define UART_TXHR	0xc	/* tx holding reg */
#define UART_INTBIT	SR_INT2

#define RXS_RXRDY	(1<<0)	/* rx ready */
#define RXS_OVR		(1<<1)	/* rx overrun */
#define RXC_IE		(1<<0)	/* interrupt enable */
#define TXS_TXRDY	(1<<0)	/* tx ready */

#define J_RA_INSTR	0x03e00008
#define SAVEAREA	0xa0000100
#define INSTR_BUFFER	0xa0000180
#define IBUFSIZE	((0xa0000300-INSTR_BUFFER)/4)


/*************************************************************
*  reset_vector:
*	This is where execution starts.
*	A maximum of 64 instructions allowed in this section
*/
	.globl _start
_start:
reset_vector: # bfc00000
	bal	cpu_init

	# make sure the sw bits of the CAUSE register are zero
	.set noreorder
	mtc0	zero,C0_CAUSE		
	.set reorder

	# enable ints in SR MASK+IEC
	li	k0,(SR_BEV|SR_IEC|UART_INTBIT)
	.set noreorder
	mtc0	k0,C0_SR
	.set reorder

	la	k0,SAVEAREA
	la	t0,get_word
	sw	t0,ICE_GWP*4(k0)
	la	t0,put_word
	sw	t0,ICE_PWP*4(k0)
	li	t0,IBUFSIZE
	sw	t0,ICE_IBS*4(k0)
	li	t0,REG_MAP
	sw	t0,ICE_MAP*4(k0)
	li	t0,SA_VERS
	sw	t0,ICE_SAV*4(k0)
	li	t0,ICE_SAHSIZE
	sw	t0,ICE_SAH*4(k0)
#ifdef MIPSEB
	li	t0,0
#else
	li	t0,1
#endif
	sw	t0,ICE_LE*4(k0)

	# print banner
        li      a0,0x44434241   # DCBA
        bal     put_word

	# wait here for the host to speak to me
#ifdef USE_NO_INTS 
   2:
	li	a2,UART_BASE

	# wait for rxrdy
   1:	lw 	k0,UART_RXS(a2)	
	and	k0,RXS_RXRDY
	beq	k0,zero,1b

	# make sure that this is a *real* attn byte
	# read the byte
	lw 	k0,UART_RXHR(a2)

#if 0   /* debug */
	not	k0

	# write the byte
	sw	k0,UART_TXHR(a2)

	b 	2b
#endif
	li	a2,ATTN
	bne	k0,a2,2b	# brif not an attn byte

	# init s0
	li	s0,INSTR_BUFFER
	b	send_ack
#else /* use ints */
#ifdef RUN_APP
	j	bspstart
#else
   1:	b	1b
#endif
#endif


/*************************************************************
* 		Start of interrupt-level code		     *
*************************************************************/
	.set noat

/*************************************************************
*  utlb_vector:
*	We should never get one of these. But just in case.
*/
	.align 8
utlb_vector: # bfc00100
	b	gen_vector

/*************************************************************
*  gen_vector:
*	All the exceptions come through here.
*/
	.align 7
	.globl gen_vector
	.ent gen_vector
gen_vector: # bfc00180
	# save regs
	la	k0,SAVEAREA
	sw	AT,ICE_AT*4(k0)
	sw	v0,ICE_V0*4(k0)
	sw	a0,ICE_A0*4(k0)
	sw	a1,ICE_A1*4(k0)
	sw	a2,ICE_A2*4(k0)
	sw	a3,ICE_A3*4(k0)

	# make sure that we are in kseg1
	la	a3,1f
	li	a2,K1BASE
	or	a3,a2
	j	a3
   1:
	sw	t0,ICE_T0*4(k0)
	sw	t1,ICE_T1*4(k0)
	sw	t2,ICE_T2*4(k0)
	sw	t3,ICE_T3*4(k0)
	sw	t4,ICE_T4*4(k0)
	sw	s0,ICE_S0*4(k0)
	sw	ra,ICE_RA*4(k0)
	.set noreorder
	mfc0	t0,C0_EPC
	nop
	.set reorder
	sw	t0,ICE_EPC*4(k0)

	# init s0 (KSEG1)
	li	s0,INSTR_BUFFER

	# read the CAUSE register
	.set noreorder
	mfc0	a0,C0_CAUSE
	nop
	.set reorder

	# hw int?
	and	t0,a0,CAUSE_EXCMASK
	bne	t0,zero,send_ack	# brif not a hw int

	# It is a hw int. But is it my int?
	.set noreorder
	mfc0	t0,C0_SR
	nop
	.set reorder
	and	t0,a0		# qualify the CAUSE bits
	and	t0,UART_INTBIT
	beq	t0,zero,send_ack	# brif not mine

	# make sure that this is a *real* attn byte
	# read the byte
	li	t0,UART_BASE
	lw	k0,UART_RXHR(t0)

	li	t0,ATTN
	bne	k0,t0,restore_rfe	# brif not an attn byte

	# fall thru
	.end gen_vector

/*************************************************************
*/
	.globl send_ack
	.ent send_ack
send_ack:
	li	t0,UART_BASE

	# make sure that the tx is ready
   1:	lw 	k0,UART_TXS(t0)
	and	k0,TXS_TXRDY
	beq	k0,zero,1b

	li	k0,ACK
	sw	k0,UART_TXHR(t0)

	# make sure that r8 and r9 are zero.
	li	t0,0
	li	t1,0
	# fall thru
	.end send_ack
	
/*************************************************************
*  ice_loop:
*	This is the main loop. We get words and process them.
*	There are 3 special types of word. 
*		1. RUN_MODE - transfer control to the customer's program.
*		2. SENDSAP  - Send the address of the SAVEAREA
*		3. SENDA0   - Execute the code in INSTR_BUFFER and send
*		              the value of register a0.
*	All other values are added to the INSTR_BUFFER.
*/
	.globl ice_loop
	.ent ice_loop
ice_loop:
	bal	get_cmd

#if 0 /* echo the input. Useful for debug */
	move	a0,v0
	bal	put_word
	b	ice_loop
#endif
   	# check for SENDA0
	li	a2,SENDA0
	bne	a2,v0,1f

	# It is SENDA0. Execute the code in INSTR_BUFFER and send 
	# the value of register a0.
	# Make sure that the routine ends with a "j ra".
	sw	zero,(s0)
	li	k0,J_RA_INSTR
	sw	k0,4(s0)
	sw	zero,8(s0)
	# Make sure that the writes complete before the jal.